參數(shù)資料
型號: S1C63455F
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP128
封裝: PLASTIC, QFP5-128
文件頁數(shù): 18/119頁
文件大小: 865K
代理商: S1C63455F
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
113
Rev. 1.0
M306H1SFP
Figure 2.11.18 Typical transmit timings in UART mode(UART2)
D0
D1
D2
D3
D4
D5
D6
D7
ST
P
Start
bit
Parity
bit
Cleared to “0” when interrupt request is accepted, or cleared by software
D0
D1
D2
D3
D4
D5
D6
D7
ST
P
Tc
SP
Stop
bit
Data is set in UART2 transmit buffer register
Transferred from UART2 transmit buffer register to UARTi transmit register
SP
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
Transmit interrupt
request bit (IR)
“0”
“1”
Transfer clock
TxD2
The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Shown in ( ) are bit symbols.
Note
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
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