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參數(shù)資料
| 型號(hào)： | S1C63406F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP128 |
| 封裝： | PLASTIC, TQFP15-128 |
| 文件頁數(shù)： | 55/144頁 |
| 文件大?。?/td> | 1160K |
| 代理商： | S1C63406F |
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10
EPSON
S1C63406 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.2 Simultaneous low input to terminals K00–K03
Another way of executing initial reset externally is to input a low signal simultaneously to the input ports
(K00–K03) selected with the mask option.
Since this initial reset passes through the noise reject circuit, maintain the specified input terminals at low
level for at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) during normal operation.
The noise reject circuit does not operate immediately after turning the power on until the oscillation
circuit starts oscillating. Therefore, maintain the specified input terminals at low level for at least 1.5 msec
(when the oscillation frequency fOSC1 is 32.768 kHz) after oscillation starts.
Table 2.2.2.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.
Table 2.2.2.1 Combinations of input ports
Not use
K00
K01K02K03
K00
K01K02
K00
K01
1
2
3
4
When, for instance, mask option 2 (K00
K01K02K03) is
selected, initial reset is executed when the signals input to the
four ports K00–K03 are all low at the same time. When 3 or 4
is selected, the initial reset is done when a key entry including
a combination of selected ports is made.
Further, the time authorize circuit can be selected with the mask option. The time authorize circuit checks
the input time of the simultaneous low input and performs initial reset if that time is the defined time (1
to 2 sec) or more.
If using this function, make sure that the specified port terminals do not go low at the same time during
ordinary operation.
2.2.3 Internal reset circuit
The S1C63406 has a built-in reset circuit that can be configured by mask option. This reset circuit provides
a system reset function when the power is instantaneously interrupted or drops as well as a power-on
reset function that is useful when the power is turned on.
Table 2.2.3.1 Reset circuit options
Use 1.8 V
Use 1.6 V
Use 1.4 V
Not use
1
2
3
4
When "Use" is selected by mask option, the reset circuit
outputs an initial reset signal to the CPU after turning the
power on until the voltage level on the VDD terminal reaches
the reset-release level. It also outputs an initial reset signal
when the power downs below the reset level.
VDD
Internal reset signal
CPU is in Run status
Level A
Level B
Power on
Fig. 2.2.3.1 Internal reset timing
A voltage level (1.8, 1.6 or 1.4 V) must be selected according to the minimum operating voltage (see Table
2.1.1) when this circuit is used. This selection presets the reset-release level (Level A) and reset level
(Level B) to the reset circuit. There is a 40 mV (Typ.) of hysteresis between Levels A and B. See Chapter 7,
"Electrical Characteristics", for the preset levels.
Note that the power-on reset circuit increases current consumption. In particular, current consumption in
reset status will be greatly increased. See Chapter 7, "Electrical Characteristics", for details.
When the "Not Use" option is selected, this circuit does not output an internal initial reset signal at power
on and down.
Note: When using the reset circuit, be sure to connect a capacitor to the reset terminal in order to
operate it properly. In this case, to avoid a large current flow in the circuit, do not fix the reset
terminal at high level.
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