參數資料
型號： RTL8150
英文描述： RTL8150L(M) Specifications
中文描述： RTL8150L（米）規(guī)格
文件頁數： 24/58頁
文件大?。?/td> 616K
代理商： RTL8150
RTL8100B(L)
2001-11-9
Rev.1.41
24
5.15 Multiple Interrupt Select Register
(Offset 005Ch-005Dh, R/W)
If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to the RTL8100B(L), RCR<ERTH[3:0]> will not be
used to transfer data in early mode. This register will be written to the received data length in order to make an early Rx interrupt
for the unfamiliar protocol.
Bit
15-12
11-0
R/W
-
R/W
Symbol
-
MISR11-0
Description
Reserved
Multiple Interrupt Select:
Indicates that the RTL8100B(L) makes an
Rx interrupt after RTL8100B(L) has transferred the byte data into the
system memory. If the value of these bits is zero, there will be no early
interrupt as soon as the RTL8100B(L) prepares to execute the first PCI
transaction of the received data. Bit1, 0 must be zero.
The ERTH3-0 bits should not be set to 0 when the multiple interrupt
select register is used.
The above is true when MulERINT=0 (bit17, RCR). When MulERINT=1, any received packet invokes early interrupt
according to MISR[11:0] setting in early mode.
5.16 PCI Revision ID
(Offset 005Eh, R)
Bit
7-0
R/W
R
Symbol
Revision ID
Description
The value in PCI Configuration Space offset 08h is 10h.
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