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參數資料
| 型號： | RJ80530NZ001256 |
| 元件分類： | 微處理器 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數： | 84/89頁 |
| 文件大小： | 1672K |
| 代理商： | RJ80530NZ001256 |
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Mobile Intel
Pentium
III Processor-M Datasheet
84
Datasheet
298340-002
TESTLO[2:1] (I - 1.5V Tolerant)
The TESTLO[2:1] (Test input Low) signals are used during processor test and needs to be pulled to
ground during normal operation.
THERMDA, THERMDC (Analog)
The THERMDA (Thermal Diode Anode) and THERMDC (Thermal Diode Cathode) signals connect
to the anode and cathode of the on-die thermal diode.
TMS (I - 1.5V Tolerant)
The TMS (Test Mode Select) signal is a JTAG support signal used by debug tools.
TRDY# (I/O - AGTL)
The TRDY# (Target Ready) signal is asserted by the target to indicate that the target is ready to receive
write or implicit write-back data transfer. TRDY# must be connected to the appropriate pins/balls on
both agents on the system bus.
TRST# (I - 1.5V Tolerant)
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The Mobile Intel Pentium
III
Processor-Ms do not self-reset during power on; therefore, it is necessary to drive this signal low
during power-on reset.
VID[4:0] (O – Open-drain)
The VID[4:0] (Voltage ID) pins/balls can be used to support automatic selection of power supply
voltages. Please refer to Section 3.2.2 for details.
VREF (Analog)
The VREF (AGTL Reference Voltage) signal provides a DC level reference voltage for the AGTL
input buffers. A voltage divider should be used to divide V
CCT
by
2
/
3
. Resistor values of 1.00 k
and
2.00 k
are recommended. Decouple the VREF signal with three 0.1-
μ
F high-frequency capacitors
close to the processor.
VTTPWRGD (I – 1.25V)
The VTTPWRGD signal informs the processor to output the VID signals. During power up, the VID
signals will be in an indeterminate state for a small period of time. The voltage regulator should not
sample and/or latch the VID signals until the VTTPWRGD signal is asserted. The assertion of the
VTTPWRGD signal indicates that the VID signals are stable and are driven to the final state by the
processor. Please refer to Figure 12 for the power up sequence.
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