參數(shù)資料
型號(hào)： RJ80530NZ001256
元件分類(lèi)： 微處理器
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 16/89頁(yè)
文件大?。?/td> 1672K
代理商： RJ80530NZ001256
Mobile Intel
Pentium
III Processor-M Datasheet
16
Datasheet
298340-002
A transition to the Deep Sleep state can be made by stopping the clock input to the processor or
asserting the DPSLP# signal. A transition back to the Normal state (from the Quick Start state) is made
only if the STPCLK# signal is deasserted.
While in the Quick Start state the processor is limited in its ability to respond to input. It is incapable
of latching any interrupts, servicing snoop transactions from symmetric bus masters or responding to
FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond
properly to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal
changes, then the behavior of the processor will be unpredictable. No serial interrupt messages may
begin or be in progress while the processor is in the Quick Start state.
RESET# assertion will cause the processor to immediately initialize itself, but the processor will stay
in the Quick Start state after initialization until STPCLK# is deasserted.
2.2.5
HALT/Grant Snoop State
The processor will respond to snoop transactions on the system bus while in the Auto Halt or Quick
Start state. When a snoop transaction is presented on the system bus the processor will enter the
HALT/Grant Snoop state. The processor will remain in this state until the snoop has been serviced and
the system bus is quiet. After the snoop has been serviced, the processor will return to its previous
state. If the HALT/Grant Snoop state is entered from the Quick Start state, then the input signal
restrictions of the Quick Start state still apply in the HALT/Grant Snoop state, except for those signal
transitions that are required to perform the snoop.
2.2.6
Deep Sleep State
The Deep Sleep state is a very low power state the processor can enter while maintaining its context.
The Deep Sleep state is entered by stopping the BCLK and BCLK# inputs to the processor or by
asserting the DPSLP# signal, while it is in the Quick Start state. Note that either one of the methods
can be used to enter Deep Sleep but
not both
at the same time. When BCLK and BCLK# are stopped,
they must obey the DC levels specified in Table 30 and Table 31.
The processor will return to the Quick Start state from the Deep Sleep state when the BCLK and
BCLK# inputs are restarted or the DPSLP# signal is deasserted. Due to the PLL lock latency, there is a
delay of up to 30
μ
sec after the clocks have started before this state transition happens. PICCLK may
be removed in the Deep Sleep state. PICCLK should be designed to turn on when BCLK and BCLK#
turn on or DPSLP# is deasserted when transitioning out of the Deep Sleep state.
2.2.7
Deeper Sleep State
The Deeper Sleep state is the lowest power state the processor can enter while maintaining its context.
It is functionally identical to the Deep Sleep State but at a lower voltage. The processor transitions to
the Deeper Sleep state from the Deep Sleep when the voltage regulator lowers the core voltage. The
VID signals for the Deeper Sleep State are supplied to the voltage regulator through control from the
I/O Controller Hub component. For more details on how this is implemented on the Mobile Intel
Pentium
III
Processor-M /Intel 830M platform, please refer to the
Intel
82801CAM I/O Controller
Hub 3 (ICH3-M) Datasheet
and contact your Intel Field Sales Representative for details on Intel
Mobile Voltage Positioning – II (IMVP-II) implementation. For details on how Deeper Sleep is
implemented on 440MX chipset based systems using the Intel SpeedStep technology Control Logic
Plus (ISSCL+) component, please refer to the
Mobile Intel
Pentium
III Processor-M/440MX
Platform Design Guide.
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