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參數(shù)資料
| 型號： | RH80530WZ014256 |
| 元件分類： | 微處理器 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 80/89頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | RH80530WZ014256 |
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Mobile Intel
Pentium
III Processor-M Datasheet
80
Datasheet
298340-002
processor will keep IERR# asserted until it is handled in software or with the assertion of RESET#,
BINIT, or INIT#.
IGNNE# (I - 1.5V Tolerant)
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error
and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor
freezes on a non-control floating-point instruction if a previous instruction caused an error. IGNNE#
has no affect when the NE bit in control register 0 (CR0) is set.
INIT# (I - 1.5V Tolerant)
The INIT# (Initialization) signal is asserted to reset integer registers inside the processor without
affecting the internal (L1 or L2) caches or the floating-point registers. The processor begins execution
at the power-on reset vector configured during power-on configuration. The processor continues to
handle snoop requests during INIT# assertion. INIT# is an asynchronous input.
If INIT# is sampled active on RESET#'s active-to-inactive transition, then the processor executes its
built-in self test (BIST).
INTR (I - 1.5V Tolerant)
The INTR (Interrupt) signal indicates that an external interrupt has been generated. INTR becomes the
LINT0 signal when the APIC is enabled. The interrupt is maskable using the IF bit in the EFLAGS
register. If the IF bit is set, the processor vectors to the interrupt handler after completing the current
instruction execution. Upon recognizing the interrupt request, the processor issues a single Interrupt
Acknowledge (INTA) bus transaction. INTR must remain active until the INTA bus transaction to
guarantee its recognition.
LINT[1:0] (I - 1.5V Tolerant)
The LINT[1:0] (Local APIC Interrupt) signals must be connected to the appropriate pins/balls of all
APIC bus agents, including the processor and the system logic or I/O APIC component. When APIC is
disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes
NMI, a non-maskable interrupt. INTR and NMI are backward compatible with the same signals for the
Pentium processor. Both signals are asynchronous inputs.
Both of these signals must be software configured by programming the APIC register space to be used
either as NMI/INTR or LINT[1:0] in the BIOS. If the APIC is enabled at reset, then LINT[1:0] is the
default configuration.
LOCK# (I/O - AGTL)
The LOCK# (Lock) signal indicates to the system that a sequence of transactions must occur
atomically. This signal must be connected to the appropriate pins/balls on both agents on the system
bus. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first
transaction through the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for bus ownership, it waits until it observes LOCK#
deasserted. This enables the processor to retain bus ownership throughout the bus locked operation and
guarantee the atomicity of lock.
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