參數(shù)資料
型號(hào)： RH80530WZ014256
元件分類： 微處理器
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 17/89頁
文件大?。?/td> 1672K
代理商： RH80530WZ014256
Mobile Intel
Pentium
III Processor-M Datasheet
298340-002
Datasheet
17
Table 2. Clock State Characteristics
Clock State
Exit Latency
Snooping
System Uses
Normal
N/A
Yes
Normal program execution
Auto Halt
10
μ
sec
Through snoop, to
HALT/Grant Snoop state:
immediate
Through STPCLK#, to
Normal state:
10 μ
sec
Yes
S/W controlled entry idle mode
Quick Start
Yes
H/W controlled entry/exit mobile throttling
HALT/Grant
Snoop
A few bus clocks after
snoop completion
Yes
Supports snooping in the low power states
Deep Sleep
30
μ
sec
No
H/W controlled entry/exit mobile powered-on
suspend support
Deeper Sleep
Platform Dependent
100
μ
sec (recommended)
No
H/W controlled entry/exit mobile powered-on
suspend support
2.2.8
Operating System Implications of Low-power States
The time-stamp counter and the performance monitor counters are not guaranteed to count in the
Quick Start state. The local APIC timer and performance monitor counter interrupts should be disabled
before entering the Deep Sleep state or the resulting behavior will be unpredictable.
2.2.9
Enhanced Intel SpeedStep Technology
The Mobile Intel Pentium
III
Processor-M supports Enhanced Intel SpeedStep technology. Enhanced
Intel SpeedStep technology allows the processor to switch between two core frequencies automatically
based on CPU demand, without having to reset the processor or change the system bus frequency. The
processor has two bus ratios programmed into it instead of one and the GHI# signal controls which one
is used. After reset, the processor will start in the lower of its two core frequencies, the “Battery
Optimized” mode. An operating mode transition to the high core frequency can be made by putting the
processor into the Deep Sleep state, raising the core voltage, setting GHI# low, and returning to the
Normal state. This puts the processor into the “Maximum performance” mode. Reversing these steps
transitions the processor back to the low-core frequency. Please contact your Intel Field Sales
Representative for details on how Enhanced Intel SpeedStep technology can be implemented with the
Mobile Intel Pentium
III
Processor-M, Intel 830MP chipset, or its equivalent.
2.3
AGTL Signals
The Mobile Pentium
III
Processor-M system bus signals use a variation of the low-voltage swing GTL
signaling technology. The AGTL system bus depends on incident wave switching and uses flight time
for timing calculations of the AGTL signals, as opposed to capacitive derating. Intel recommends
analog signal simulation of the system bus including trace lengths. Contact your field sales
representative to receive the IBIS models for the Mobile Pentium
III
Processor-M.
The AGTL system bus of the Mobile Pentium
III
Processor-M is designed to support high-speed data
transfers with multiple loads on a long bus that behaves like a transmission line. This termination is
provided on the processor core (except for the RESET# signal).
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