參數(shù)資料
型號(hào)： RH80530NZ004256
英文描述： MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC
中文描述： 微處理器| 32位|的CMOS |美巡賽| 478PIN |陶瓷
文件頁(yè)數(shù)： 75/89頁(yè)
文件大?。?/td> 1672K
代理商： RH80530NZ004256
Mobile Intel
Pentium
III Processor-M Datasheet
298340-002
Datasheet
75
8.
Processor Interface
8.1
Alphabetical Signal Reference
A[35:3]# (I/O – AGTL)
The A[35:3]# (Address) signals define a 2
36
-byte physical memory address space. When ADS# is
active, these signals transmit the address of a transaction; when ADS# is inactive, these signals
transmit transaction information. These signals must be connected to the appropriate pins/balls of both
agents on the system bus. The A[35:24]# signals are protected with the AP1# parity signal, and the
A[23:3]# signals are protected with the AP0# parity signal.
On the active-to-inactive transition of RESET#, each processor bus agent samples A[35:3]# signals to
determine its power-on configuration. See
P6 Family of Processors Developer’s Manual
for details.
A20M# (I - 1.5V Tolerant)
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks physical address bit 20
(A20#) before looking up a line in any internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary.
Assertion of A20M# is only supported in Real mode.
ADS# (I/O - AGTL)
The ADS# (Address Strobe) signal is asserted to indicate the validity of a transaction address on the
A[35:3]# signals. Both bus agents observe the ADS# activation to begin parity checking, protocol
checking, address decode, internal snoop or deferred reply ID match operations associated with the
new transaction. This signal must be connected to the appropriate pins/balls on both agents on the
system bus.
AERR# (I/O - AGTL)
The AERR# (Address Parity Error) signal is observed and driven by both system bus agents, and if
used, must be connected to the appropriate pins/balls of both agents on the system bus. AERR#
observation is optionally enabled during power-on configuration; if enabled, a valid assertion of
AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent may handle an
assertion of AERR# as appropriate to the error handling architecture of the system.
AP[1:0]# (I/O - AGTL)
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#, A[35:3]#,
REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. A correct parity signal is high if
an even number of covered signals is low and low if an odd number of covered signals are low. This
allows parity to be high when all the covered signals are high. AP[1:0]# should be connected to the
appropriate pins/balls on both agents on the system bus.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RH80530NZ006256 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC
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