- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372063 > RH80530NZ001256 Microprocessor PDF資料下載
參數(shù)資料
| 型號： | RH80530NZ001256 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 81/89頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | RH80530NZ001256 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁當前第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁
Mobile Intel
Pentium
III Processor-M Datasheet
298340-002
Datasheet
81
NC (No Connect)
All signals named NC (No Connect) must be left unconnected.
NCTRL (I - Analog)
The NCTRL signal provides the AGTL pull down impedance control. The processor samples this
input to determine the N-channel pull-down device strength when it is the driving agent. An external
14 ohm (1% tolerance) pull-up resistor to V
CCT
is required for this signal. Please refer to platform
design guide for implementation details.
NMI (I - 1.5V Tolerant)
The NMI (Non-Maskable Interrupt) indicates that an external interrupt has been generated. NMI
becomes the LINT1 signal when the APIC is disabled. Asserting NMI causes an interrupt with an
internally supplied vector value of 2. An external interrupt-acknowledge transaction is not generated. If
NMI is asserted during the execution of an NMI service routine, it remains pending and is recognized
after the IRET is executed by the NMI service routine. At most, one assertion of NMI is held pending.
NMI is rising edge sensitive.
PICCLK (I – 1.8V Tolerant)
The PICCLK (APIC Clock) signal is an input clock to the processor and system logic or I/O APIC that
is required for operation of the processor, system logic, and I/O APIC components on the APIC bus.
PICD[1:0] (I/O - 1.5V Tolerant Open-drain)
The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC
bus. They must be connected to the appropriate pins/balls of all APIC bus agents, including the
processor and the system logic or I/O APIC components. If the PICD0 signal is sampled low on the
active-to-inactive transition of the RESET# signal, then the APIC is hardware disabled. For the
Mobile Intel Pentium
III
Processor-M, the APIC is required to be hardware enabled as described in
Section 7.1.3
PLL1, PLL2 (Analog)
The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL. See
Section 3.2.2 for a description of the analog decoupling circuit.
PRDY# (O - AGTL)
The PRDY# (Probe Ready) signal is a processor output used by debug tools to determine processor
debug readiness.
PREQ# (I - 1.5V Tolerant)
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processor.
PWRGOOD (I – 1.8V Tolerant)
PWRGOOD (Power Good) is a 1.8-V tolerant input. The processor requires this signal to be a clean
indication that clocks and the power supplies (V
CC
, V
CCT
, etc.) are stable and within their
specifications. Clean implies that the signal will remain low, (capable of sinking leakage current) and
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RH80530NZ004256 | MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| RH80530NZ006256 | MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| RH80530NZ009256 | MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| RH80530WZ014256 | Microprocessor |
| RJ80530GZ009512 | Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RH80530NZ001256S L6AB | 制造商:Intel 功能描述:MPU Celeron? Processor 64-Bit 0.13um 1GHz 478-Pin uFCPGA |
| RH80530NZ004256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| RH80530NZ006256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| RH80530NZ009256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| RH80530NZ012256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。