
élanSC400 Microcontroller Register Set Reference Manual Amendment
9
A M E N D M E N T
3-53
PMU Present and Last
Mode Register, Index
41h; bit 6 description
Set this bit to immediately time out
the current mode timer. This bit does
not need to be cleared and is not
read back. Software should not
invoke this feature for at least 15
microseconds after a wake-up from
Suspend mode. Software can read
the last mode from bits 5–3 of this
register and delay 15 microseconds
if the last mode was Suspend mode
before setting this bit.
Set this bit to force an immediate
time-out of the current mode timer,
causing the PMU to drop to the next
lower speed. This bit does not need to
be cleared and is not read back. This
function is designed for debugging
power management software.
Software should not invoke this
feature for at least one 32-KHz clock
cycle (30.5
μ
s) after a wake-up from
Suspend mode. Software can read
the last mode from bits 5–3 of this
register and delay 30.5
μ
s if the last
mode was Suspend mode before
setting this bit.
Expand
description.
Increase delay.
Forced time-out
might be missed
(bit not latched)
if used too soon
after wake-up
from Suspend
mode.
3-57
Wake-Up Pause/High-
Speed Clock Timers
Register, Index 45h;
bits 2–0 description
Timer value to count down after a
wake up is sensed and the PLLs are
started up (if necessary) and the
GPIO_CSx signals are switched to
High-Speed (or Low-Speed) mode
levels (for those GPIO_CSx signals
that are programmed to change
based on PMU mode) to allow the
power supplies to stabilize before the
élanSC400 microcontroller starts
driving its outputs or using its inputs.
Read returns the last value written.
Selects the required delay from the
time a wake-up is sensed and the
PLLs are started up to allow the
power supplies to stabilize before the
microcontroller begins driving its
outputs or using its inputs. Read
returns the last value written.
Rewrite.
Remove
reference to
programmed
GPIO_CSx
signals. All chip
functions are
delayed.
3-59
Wake-Up Source
Enable Register A,
Index 52h; diagram, (bit
3 column)
Reserved
0
R/W
Reserved
x
Correction.
Wake-Up Source
Enable Register A,
Index 52h; bit 3
description
Reserved
Reserved
During read/modify/write operations,
software must preserve this bit.
Correct
omission.
3-61
Wake-Up Source
Enable Register C,
Index 54h; diagram
(bits 7–6 columns)
PDRQ1_WAKE
0
R/W
PDRQ0_WAKE
0
R/W
RESERVED
x
RESERVED
x
DMA requests
do not support
wake-ups.
Wake-Up Source
Enable Register C,
Index 54h; bit 7
description
PDRQ1_WAKE
Programmable DMA Request 1
(PDRQ1) Wake-Up Control
0 = Do not wake up system
1 = Wake up system
Reserved
Reserved
DMA requests
do not support
wake-ups.
Wake-Up Source
Enable Register C,
Index 54h; bit 6
description
PDRQ0_WAKE
Programmable DMA Request 0
(PDRQ0) Wake-Up Control
0 = Do not wake up system
1 = Wake up system
Reserved
Reserved
DMA requests
do not support
wake-ups.
Table 1.
Corrections to the
élanSC400 Microcontroller Register Set Reference Manual
(Continued)
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