I Peripheral Control Interconnect (PCI) Compatible with PCI bus operating speeds of 33MHz/" />
參數(shù)資料
型號： R8J73437BGZV
廠商： Renesas Electronics America
文件頁數(shù)： 8/46頁
文件大?。?/td> 0K
描述： SH-MOBILE 3AS
產(chǎn)品培訓(xùn)模塊： Electromagnetic Noise Reduction Techniques Part 1
標準包裝： 1
系列： SH-Mobile
核心處理器： SH-4A
芯體尺寸： 32-位
速度： 216MHz
連通性： I²C
外圍設(shè)備： DMA，LCD，WDT
輸入/輸出數(shù)： 176
程序存儲器類型： ROMless
RAM 容量： 16M x 8
電壓 - 電源 (Vcc/Vdd)： 1.1 V ~ 1.3 V
封裝/外殼： 模塊
包裝： 托盤
Peripherals
I Peripheral Control Interconnect (PCI)
Compatible with PCI bus operating
speeds of 33MHz/66MHz
Compatible with 32-bit PCI bus
Up to four PCI master devices running at
33MHz, or one PCI master device at
66MHz, can be connected
Arbitration control is available as a PCI
host function
Can operate as master or target
When operating as master, PIO and
DMA transfer are available
Four DMA transfer channels
Six 32-bit x 16 longword internal FIFO
(one for target reading, one for target
writing, and four for DMA transfer)
SRAM, DRAM, SDRAM, DDR-SDRAM,
and MPX can be used as external memory
for PCI bus data transfers
32-bit or 16-bit memory data bus for data
transfers with PCI bus (32-bit bus when
connected to SDRAM or DDR-SDRAM)
Support for big-endian and little-endian
local bus (PCI bus operates with little
endian, while internal bus for peripheral
modules operates with big endian)
I DMA Controller (DMAC)
Up to twelve channels
Choice of 8-bit, 16-bit, 32-bit, 64-bit, or
32-byte transfer data length
Choice of address mode; single or dual;
choice of bus mode: cycle steal mode or
burst mode
Two types of DMAC channel priority
ranking: fixed-priority mode and round-
robin mode
14
SuperH
Family of Microcontrollers & Microprocessors
Interrupt
Control
Local
Register
PCI Bus
PCI
Configuration
Register
PCI Bus Interface
Internal
Peripheral
Module Bus
Interface
Local
Register
FIFO
32B (2 sides)6
Data Transfer Control
Local
register
Bus Request
Acknowledge
Local
Register
PCIC Bus Controller
PCI Clock
33/66 MHz
(PCICLK)
Local Bus
Feedback
Input Clock
from CKIO
Local Bus Clock
(Bf ) Cycle: Bcyc
Interrupts
PCIC Module
(Peripheral Bus)
Internal Peripheral
Module Bus
PCI Block Diagram
DMAC
DACK
External
memory
External
device
with DACK
SuperH Device
External
address
bus
: Data flow
External
data bus
SINGLE-ADDRESS MODE: Parallel read and write
DUAL-ADDRESS MODE: Two-cycle read and write
Data Buffer
SAR
DAR
DMAC
BSC
SuperH device
Addr
e
ss
bu
s
Data
bu
s
Memory
Transfer Source
Module
2nd bus cycle: Taking the DAR value as the address, the data stored
in the BSC's data buffer is written to the transfer destination module.
1st bus cycle: Taking the SAR value as the address, data is read
from the transfer source module and stored temporarily in the
data buffer in the Bus State Controller (BSC).
Data Buffer
Addr
e
ss
bu
s
Data
bu
s
Memory
SAR
DA R
DMAC
BSC
SuperH device
Transfer Destination
Module
Transfer Destination
Module
Transfer Source
Module
DMAC: Single and Dual Address Modes
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