Family of Microcontrollers & Microprocessors I SH" />
參數(shù)資料
型號(hào): R8J73437BGZV
廠商: Renesas Electronics America
文件頁(yè)數(shù): 45/46頁(yè)
文件大?。?/td> 0K
描述: SH-MOBILE 3AS
產(chǎn)品培訓(xùn)模塊: Electromagnetic Noise Reduction Techniques Part 1
標(biāo)準(zhǔn)包裝: 1
系列: SH-Mobile
核心處理器: SH-4A
芯體尺寸: 32-位
速度: 216MHz
連通性: I²C
外圍設(shè)備: DMA,LCD,WDT
輸入/輸出數(shù): 176
程序存儲(chǔ)器類型: ROMless
RAM 容量: 16M x 8
電壓 - 電源 (Vcc/Vdd): 1.1 V ~ 1.3 V
封裝/外殼: 模塊
包裝: 托盤
6
SuperH
Family of Microcontrollers & Microprocessors
I SH-2A Family Features
Instruction set upward compatible
with SuperH RISC Family
Upward compatible with SH-1 and
SH-2 Family of devices
Compact 16/32-bit instruction code
Flexible addressing modes.
Integrated SH-2A CPU engine and FPU
optimized for performance, low power
and cost
Improved performance
– 1.5x performance compared to
SH-2 architecture
Better code density
– 75% code-size reduction compared
to SH-2 core
Real-time control
– 6-cycle interrupt-response time
Floating Point Unit (FPU):
– 1.4 GFlops performance
SH-2A CPU Architecture
Superscalar RISC engine
32-bit Harvard architecture
5-stage RISC CPU pipeline
Instruction/Data cache
2-instruction/cycle execution time
Conditional delayed branching
Flexible addressing modes
On-chip multiplier unit
supports MAC operations
Prioritized exception handling
SH-2A FPU Architecture
Supports IEEE-754 compliant
data types and exceptions
Independent 5-stage pipeline
Single/double-precision operation
support
16 x 32-bit floating point registers
Supports FMAC/FDIV/FMUL/FSQRT
instructions
Abundant Registers
16 x 32-bit general-purpose
– R0 - R15
4 x 32-bit system registers
– (MACH/L) High/Low
Multiply & Accumulate registers
– (PR) Procedure register
– (PC) Program counter register
4 x 32-bit control registers
– (SR) Status register
– (GBR) Global base register
– (VBR) Vector base register
– (TBR) Jump-table base register
16 x 32-bit Floating Point Registers
– FPR0 - FPR15
Register banks
– Allow contents of general registers
R0 to R14, global register (GBR),
the multiply and accumulate registers
(MACH, MACL), the procedure
register (PR), and the interrupt
vector table address offsets (VTO) to
be banked during interrupts
Improved Instruction Set
16-bit basic instructions
for improved efficiency
32-bit instructions for
improved performance
Delayed branch instructions.
Register bank instructions for
improved interrupt latency
Barrel shift instructions supporting
logical and arithmetic operations
Multiple register save/restore
instructions
Instruction set based on C language
for ease of development
Easier to program; simplified
product development
Multitasking instead of
multiprocessing
Eliminates inter-processor
communication
Single hardware/software
design environment
IF
ID
DF
EX
MA
WB
EX
E1
E2
SF
EX
NA
SF
mm
WB
E1
SH-2A
CPU
FPU
IBUS
DATA
IF
ID
SH-2A CPU Architecture
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