參數(shù)資料
型號: R8J73437BGZV
廠商: Renesas Electronics America
文件頁數(shù): 35/46頁
文件大?。?/td> 0K
描述: SH-MOBILE 3AS
產(chǎn)品培訓模塊: Electromagnetic Noise Reduction Techniques Part 1
標準包裝: 1
系列: SH-Mobile
核心處理器: SH-4A
芯體尺寸: 32-位
速度: 216MHz
連通性: I²C
外圍設(shè)備: DMA,LCD,WDT
輸入/輸出數(shù): 176
程序存儲器類型: ROMless
RAM 容量: 16M x 8
電壓 - 電源 (Vcc/Vdd): 1.1 V ~ 1.3 V
封裝/外殼: 模塊
包裝: 托盤
Appendices
38
LEGEND:
ADC:
ASERAM:
AUD:
BSC:
CACHE:
CCN:
CMT:
CPG/WDT:
CPU:
DAC:
DMAC:
DSP:
UDI:
INTC:
A/D converter
ASE memory
Advanced user debugger
Bus state controller
Cache memory
Cache memory controller
Compare match timer
Clock pulse generator/watchdog timer
Central processing unit
D/A converter
Direct memory access controller
Digital signal processor
User debugging interface
Interrupt controller
IrDA:
MMU:
RTC:
SCI:
SCIF:
TLB:
TMU:
UBC:
XYCNT:
XYMEM:
Serial communicatiion interface (with IRDA)
Memory management unit
Realtime clock
Serial communication interface
(with smart card interface)
Serial communication interface (with FIFO)
Translation look-aside buffer
Timer unit
User break controller
X/Y memory controller
X/Y memory
SH-3, SH3-DSP Architecture
= SH3-DSP only
XYCNT
XYMEM
MMU
TLB
SH-3
CPU
DSP
UBC
SCI
TMU
RTC
IrDA
SCIF
ADC
DAC
AUD
DMAC
CMT
I/O port
External bus
interface
BSC
CCN
CACHE
ASERAM
H-UDI
INTC
CPG/WDT
Peripheral
bu
s
1
Peripheral
bu
s
2
Ibu
s
L
bu
s
Y
bu
s
X
bu
s
I Appendix A-3: Architecture of SH-3, SH3-DSP, and SH-4 Series
SH-4 Architecture
BSC:
Bus state controller
CPG:
Clock pulse generator
DMAC: Direct memory access controller
FPU:
Floating-point unit
INTC:
Interrupt controller
ITLB:
Instruction TLB (translation lookaside buffer)
UTLB:
Unified TLB (translation lookaside buffer)
RTC:
Realtime clock
SCI:
Serial communication interface
SCIF:
Serial communication interface with FIFO
TMU:
Timer unit
UBC:
User break controller
PCIC:
PCI bus controller
Lower 32-bit data
64-bit
data
(
s
tor
e
)
CPG
INTC
SCI
(SCIF)
RTC
TMU
External (SH) bus
interface
DMAC
32-bit
data
29-bit
addr
e
ss
32-bit
data
Addr
e
ss
32-bit
data
32-bit
data
Upper
32-bit
data
32-bit
addr
e
ss
(in
s
truction
s
)
32-bit
data
(in
s
truction
s
)
32-bit
addr
e
ss
(data)
Peripheral
data
bu
s
26-bit
SH bus
address
32-bit
PCI
address/
data
32-bit SH bus data
(64-bit for SH7751)
Peripheral
addr
e
ss
bu
s
UBC
32-bit
data
(
s
tor
e
)
32-bit
data
(load)
SH-4 CPU
I cache
(8 kB)
O cache
(16 kB)
ITLB
UTLB
Cache and
TLB
controller
FPU
32-bit
data
PCIC
BSC
Addr
e
ss
(PCI)DMAC
= SH7751R only
LEGEND:
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