參數(shù)資料
型號： R5F56218BDLD#U0
廠商： Renesas Electronics America
文件頁數(shù)： 99/148頁
文件大?。?/td> 0K
描述： MCU 32BIT FLASH 512K ROM 85TFLGA
產(chǎn)品培訓模塊： RX USB Peripheral
CAN Peripheral and API
RX 12-Bit ADC
RX Bus State Controller
RX Low Voltage Detection and Reset Sources
RX Watchdog Timer
RX 10-Bit ADC
RX 10-Bit DAC
RX Core
RX Compare Match Timer
RX DMAC
特色產(chǎn)品： RX600 Series Microcontrollers
標準包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： CAN，EBI/EMI，I²C，SCI，SPI，USB
外圍設備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 58
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10/12b，D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 85-TFLGA
包裝： 托盤
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 52
2004 Microchip Technology Inc.
TABLE 4-3:
REGISTER FILE SUMMARY
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
TOSU
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
STKPTR
STKFUL
STKUNF
—
Return Stack Pointer
00-0 0000
PCLATU
—
bit 21
Holding Register for PC<20:16>
--10 0000
PCLATH
Holding Register for PC<15:8>
0000 0000
PCL
PC Low Byte (PC<7:0>)
0000 0000
TBLPTRU
—
—bit 21(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
TABLAT
Program Memory Table Latch
0000 0000
PRODH
Product Register High Byte
xxxx xxxx
PRODL
Product Register Low Byte
xxxx xxxx
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
1111 1111
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
1100 0000
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
n/a
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented
(not a physical register)
n/a
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented
(not a physical register)
n/a
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
n/a
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented
(not a physical register) – value of FSR0 offset by value in WREG
n/a
FSR0H
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
WREG
Working Register
xxxx xxxx
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
n/a
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented
(not a physical register)
n/a
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented
(not a physical register)
n/a
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented
(not a physical register)
n/a
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented
(not a physical register) – value of FSR1 offset by value in WREG
n/a
FSR1H
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
BSR
—
Bank Select Register
---- 0000
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
n/a
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented
(not a physical register)
n/a
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented
(not a physical register)
n/a
Legend:
x
= unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
2:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
3:
These registers are unused on PIC18F6X20 devices; always maintain these clear.
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