參數(shù)資料
型號(hào): R5F56218BDLD#U0
廠商: Renesas Electronics America
文件頁數(shù): 12/148頁
文件大?。?/td> 0K
描述: MCU 32BIT FLASH 512K ROM 85TFLGA
產(chǎn)品培訓(xùn)模塊: RX USB Peripheral
CAN Peripheral and API
RX 12-Bit ADC
RX Bus State Controller
RX Low Voltage Detection and Reset Sources
RX Watchdog Timer
RX 10-Bit ADC
RX 10-Bit DAC
RX Core
RX Compare Match Timer
RX DMAC
特色產(chǎn)品: RX600 Series Microcontrollers
標(biāo)準(zhǔn)包裝: 1
系列: RX600
核心處理器: RX
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,SCI,SPI,USB
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 58
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10/12b,D/A 1x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 85-TFLGA
包裝: 托盤
2004 Microchip Technology Inc.
DS39609B-page 107
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-6:
BLOCK DIAGRAM OF RB2:RB0 PINS
FIGURE 10-7:
BLOCK DIAGRAM OF RB3 PIN
Data Latch
RBPU(2)
P
VDD
Q
D
CK
Q
D
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Weak
Pull-up
RD Port
INTx
I/O pin(1)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note
1:
I/O pins have diode protection to VDD and VSS.
2:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
Data Latch
P
VDD
Q
D
CK
Q
D
EN
Data Bus
WR LATB or
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
CCP2 or INT3
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
RD LATB
WR PORTB
RBPU(2)
CK
D
Enable(3)
CCP Output
RD PORTB
CCP Output(3)
1
0
P
N
VDD
VSS
I/O pin(1)
Q
CCP2MX
CCP2MX = 0
Note
1:
I/O pin has diode protection to VDD and VSS.
2:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
3:
The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device
is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.
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