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參數(shù)資料
| 型號： | R2051K |
| 英文描述： | real-time clock ICs |
| 中文描述： | 實時時鐘IC |
| 文件頁數(shù)： | 34/53頁 |
| 文件大?。?/td> | 343K |
| 代理商： | R2051K |
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R2051 Series
When setting DEV bit to 1:
Oscillation adjustment value = (32768.85 - 32768.05 + 0.0333) / (32768.85
×
1.017
×
10
-6
)
≈
(32768.85 - 32768.05)
×
30 + 1
= 23.51
≈
24
In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(1,0,0,1,1,0,0,0) in the oscillation adjustment
register.
(B) For an oscillation frequency = 32762.22Hz and a target frequency = 32768.05Hz
When setting DEV bit to 0:
Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22
×
3.051
×
10
-6
)
≈
(32762.22 - 32768.05)
×
10
= -58.325
≈
-58
To represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3Ah) from 128
(80h) to obtain 46h. In this instance, write the settings of (DEV,F6,F5,F4,F3,F2,F1,F0) = (0,1,0,0,0,1,1,0) in the
oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count
loss represents a distance from 80h.
When setting DEV bit to 1:
Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22
×
1.017
×
10
-6
)
≈
(32762.22 - 32768.05)
×
30
= -174.97
≈
-175
Oscillation adjustment value can be set from -62 to 63. Then, in this case, Oscillation adjustment value is out of
range.
(4) Difference between DEV=0 and DEV=1
Difference between DEV=0 and DEV=1 is following,
DEV=0
Maximum valluerange
-189.2ppm to 189.2ppm
Minimum resolution
3ppm
Notes:
1)
Oscillation adjustment does not affect the frequency of 32.768-kHz clock pulses output from the
CLKOUT pin.
2)
Oscillation adjustment value range: When the oscillation frequency is higher than the target frequency
(causing a time count gain), an appropriate time count gain ranges from -3.05ppm to -189.2ppm with the
settings of "0, 0, 0, 0, 0, 1, 0" to "0, 1, 1, 1, 1, 1, 1" written to the F6, F5, F4, F3, F2, F1, and F0 bits in
the oscillation adjustment register, thus allowing correction of a time count gain of up to +189.2ppm.
Conversely, when the oscillation frequency is lower than the target frequency (causing a time count
loss), an appropriate time count gain ranges from +3.05ppm to +189.2ppm with the settings of "1, 1, 1,
1, 1, 1, 1" to "1, 0, 0, 0, 0, 1, 0" written to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation
adjustment register, thus allowing correction of a time count loss of up to -189.2ppm.
G
How to evaluate the clock gain or loss
The oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the
oscillation adjustment register once in 20 seconds or 60 seconds. The oscillation adjustment circuit does not
effect the frequency of 32768Hz-clock pulse output from the CLKOUT pin. Therefore, after writing the oscillation
adjustment register, we cannot measure the clock error with probing CLKOUT clock pulses. The way to measure
the clock error as follows:
(1) Output a 1Hz clock pulse of Pulse Mode with interrupt pin
Set (0,0,x,x,0,0,1,1) to Control Register 1 at address Eh.
12345
Rev.1.04 - 34 -
DEV=1
--62ppm to 63ppm
1ppm
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