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R2051 Series
12345
Rev.1.04 - 15 -
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of
±
3.784 ms.
Control Register 2 (Address Fh)
D7
D6
D5
D4
D3
VDSL
VDET
/XST
PON
SCRA
TCH1
VDSL
VDET
/XST
PON
SCRA
TCH1
0
0
Indefinite
1
0
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
G
D2
CTFG
D1
WAFG
D0
DAFG
(For Writing)
CTFG
WAFG
DAFG
(For Reading)
0
0
0
Default Settings *)
(1) VDSL
VDD Supply Voltage Monitoring Threshold Selection Bit
Description
Selecting the VDD supply voltage monitoring threshold setting of 2.1v.
Selecting the VDD supply voltage monitoring threshold setting of 1.35v.
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
VDSL
0
1
(Default)
(2) VDET
Supply Voltage Monitoring Result Indication Bit
Description
Indicating supply voltage above the supply voltage monitoring threshold
settings.
Indicating supply voltage below the supply voltage monitoring threshold
settings.
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold
the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring
circuit. Conversely, setting the VDET bit to 1 causes no event.
(3) /XST
Oscillation Halt Sensing Monitor Bit
/XST
Description
0
Sensing a halt of oscillation
1
Sensing a normal condition of oscillation
The /XST accepts the reading and writing of 0 and 1. The /XST bit will be set to 0 when the oscillation halt
sensing. The /XST bit will hold 0 even after the restart of oscillation.
(4) PON
Power-on-reset Flag Bit
PON
Description
0
Normal condition
1
Detecting VDD power-on -reset
The PON bit is for sensing power-on reset condition.
*
The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1
even after power-on.
*
When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control
Register 1, and Control Register 2, except /XST and PON. As a result, /INTR pin stops outputting.
*
The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.
(5) SCRATCH1
Scratch Bit 1
SCRATCH1
Description
0
1
The SCRATCH1 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH1
bit
will be set to 0 when the PON bit is set to 1 in the Control Register 2.
VDET
0
(Default)
1
(Default)
(Default)