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參數(shù)資料
| 型號： | R2051K |
| 英文描述： | real-time clock ICs |
| 中文描述： | 實時時鐘IC |
| 文件頁數(shù)： | 14/53頁 |
| 文件大?。?/td> | 343K |
| 代理商： | R2051K |
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R2051 Series
(5) CT2, CT1, and CT0
CT2
12345
Rev.1.04 - 14 -
Periodic Interrupt Selection Bits
Description
CT0
Wave
mode
0
-
1
-
0
Pulse Mode
*1)
1
Pulse Mode
*1)
0
Level Mode
*2)
1
Level Mode
*2)
0
Level Mode
*2)
1
Level Mode
*2)
CT1
form
Interrupt Cycle and Falling Timing
0
0
0
0
0
1
OFF(H)
Fixed at “L”
2Hz (Duty50%)
(Default)
0
1
1Hz (Duty50%)
1
0
Once per 1 second (Synchronized with
second counter increment)
Once per 1 minute (at 00 seconds of every
minute)
Once per hour (at 00 minutes and 00
seconds of every hour)
Once per month (at 00 hours, 00 minutes,
and 00 seconds of first day of every
month)
1
0
1
1
1
1
* 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second
counter as illustrated in the timing chart below.
/INTR Pin
Rewriting of the second counter
CTFG Bit
Approx. 92
μ
s
(Increment of second counter)
In the pulse mode, the increment of the second counter is delayed by approximately 92
μ
s from the
falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock
pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the /INTR
pin low.
* 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1
minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling
edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting
of 1 second are output in synchronization with the increment of the second counter as illustrated in the
timing chart below.
CTFG Bit
(Increment of
second counter)
Setting CTFG bit to 0
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
/INTR Pin
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or
60sec. as follows:
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of
±
3.784 ms. For
example, 1-Hz clock pulses will have a duty cycle of 50
±
0.3784%.
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| R2051K01-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:2 wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
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| R2051S01-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:2 wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
| R2051S02-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:2 wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
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