參數(shù)資料
型號(hào)： QL6325-4PB516C
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 1536 CLBS, 320640 GATES, PBGA516
封裝： 1.27 MM PITCH, PLASTIC, BGA-516
文件頁(yè)數(shù)： 17/38頁(yè)
文件大?。?/td> 1093K
代理商： QL6325-4PB516C
24
2002 QuickLogic Corporation
QL6325 Eclipse Data Sheet Rev C
Recommended Unused Pin Terminations for the Eclipse devices
All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance)
internally using the Configuration Editor. This option is given in the bottom-right corner of
the placement window. To use the Placement Editor, choose Constraint
Fix Placement
in the Option pull-down menu of SpDE.
The rest of the pins should be terminated at the board level in the manner presented in
NOTE: x -> number, y -> alphabetical character.
Ordering Information
Figure 26: Ordering Information
Table 18: Recommended Unused Pin Terminations
Signal Name
Recommended Termination
PLLOUT<x>
Unused PLL output pins must be connected to either V
CC or GND so that their associated
input buffer never floats. Utilized PLL output pins that route the PLL clock outside of the
chip should not be tied to either V
CC or GND.
IOCTRL<y>
Any unused pins of this type must be connected to either V
CC or GND.
CLK/PLLIN<x>
Any unused clock pins should be connected to VCC or GND.
PLLRST<x>
If a PLL module is not used, then the associated PLLRST<x> must be connected to V
CC,
under normal operation use it as needed.
INREF<y>
If an I/O bank does not require the use of INREF signal the pin should be connected to
GND.
QL 6325 - 4 PB516 C
QuickLogic device
Eclipse device
part number
Speed Grade
4 = Quick
5 = Fast
6 = Faster
7 = Fastest
Operating Range
C = Commercial
I = Industrial
M = Military
Package Code
PT208 = 208-pin FPBGA
PT280 = 280-pin FPBGA
PS484 = 484-pin BGA (1.0 mm)
PB516 = 516-pin BGA (1.27 mm)
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