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參數(shù)資料
| 型號： | QL6325-4PB516C |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1536 CLBS, 320640 GATES, PBGA516 |
| 封裝： | 1.27 MM PITCH, PLASTIC, BGA-516 |
| 文件頁數(shù)： | 15/38頁 |
| 文件大?。?/td> | 1093K |
| 代理商： | QL6325-4PB516C |
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22
2002 QuickLogic Corporation
QL6325 Eclipse Data Sheet Rev C
Pin Descriptions
Figure 25: I/O Banks with Relevant Pins
Table 16: JTAG Pin Descriptions
Pin
Function
Description
TDI/RSI
Test Data In for JTAG/RAM
init. Serial Data In
Hold HIGH during normal operation. Connects to serial PROM
data in for RAM initialization. Connect to V
CC if unused
TRSTB/RRO
Active low Reset for
JTAG/RAM init. reset out
Hold LOW during normal operation. Connects to serial PROM
reset for RAM initialization. Connect to GND if unused
TMS
Test Mode Select for JTAG
Hold HIGH during normal operation. Connect to V
CC if not used
for JTAG
TCK
Test Clock for JTAG
Hold HIGH or LOW during normal operation. Connect to V
CC or
ground if not used for JTAG
TDO/RCO
Test data out for JTAG/RAM
init. clock out
Connect to serial PROM clock for RAM initialization. Must be left
unconnected if not used for JTAG or RAM initialization
IO BANK A
IO BANK B
V CCI
O
(A
)
IN
R
E
F(
A)
IO
C
TR
L(
A
)
IO
(A
)
V CCI
O
(A
)
IN
R
E
F(
A)
IO
C
TR
L(
A
)
IO
(A
)
IO
BAN
K
C
IO
BAN
K
D
VCCIO (C)
INREF(C)
IOCTRL(C)
IO(C)
VCCIO(D)
INREF(D)
IOCTRL(D)
IO(D)
IO BANK F
IO BANK E
VCCI
O
(F
)
IN
R
E
F(
F)
IO
CT
RL(F
)
IO
(F
)
VCCI
O
(E
)
IN
R
E
F(E)
IO
CT
RL(E
)
IO
(E
)
IO
BAN
K
H
IO
BAN
K
G
(H)
INREF(H)
IOCTRL(H)
IO(H)
VCCIO
(G)
INREF(G)
IOCTRL(G)
IO(G)
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