參數(shù)資料
型號: QL6325-4PB516C
廠商: QUICKLOGIC CORP
元件分類: FPGA
英文描述: FPGA, 1536 CLBS, 320640 GATES, PBGA516
封裝: 1.27 MM PITCH, PLASTIC, BGA-516
文件頁數(shù): 12/38頁
文件大?。?/td> 1093K
代理商: QL6325-4PB516C
2
2002 QuickLogic Corporation
QL6325 Eclipse Data Sheet Rev C
Electrical Specifications
AC Characteristics at V
CC = 2.5 V, TA = 25° C (K = 0.74)
The AC Specifications are provided from Table 1 to Table 10. Logic Cell diagrams and
waveforms are provided from Figure 2 to Figure 15.
Figure 2: Eclipse Logic Cell
Table 1: Logic Cells
Symbol
Parameter
Value (ns)
Logic Cells
Min
Max
t
PD
Combinatorial Delay of the longest path: time taken by the combinatorial circuit to
output
-
0.257
t
SU
Setup time: time the synchronous input of the flip flop must be stable before the
active clock edge
0.22
-
tHL
Hold time: time the synchronous input of the flip flop must be stable after the active
clock edge
0
-
t
CO
Clock-to-out delay: the amount of time taken by the flip flop to output after the
active clock edge.
-
0.255
t
CWHI
Clock High Time: required minimum time the clock stays high
0.46
-
t
CWLO
Clock Low Time: required minimum time that the clock stays low
0.46
-
tSET
Set Delay: time between when the flip flop is ”set” (high)
and when the output is consequently “set” (high)
-
0.18
t
RESET
Reset Delay: time between when the flip flop is ”reset” (low) and when the output
is consequently “reset” (low)
-
0.09
tSW
Set Width: time that the SET signal remains high/low
0.3
-
t
RW
Reset Width: time that the RESET signal remains high/low
0.3
-
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