參數(shù)資料
型號(hào)： PXAC37
廠商： NXP Semiconductors N.V.
英文描述： XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce
中文描述： 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個(gè)SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce
文件頁(yè)數(shù)： 59/68頁(yè)
文件大?。?/td> 368K
代理商： PXAC37
Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
52
MCPLH
15
Obj31
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Obj30
Obj29
Obj28
Obj27
Obj26
Obj25
Obj24
Obj23
Obj22
Obj21
Obj20
Obj19
Obj18
Obj17
Obj16
MCPLL (Message Complete Status Flags Low)
Address: MMR base + 224h
Access: Read/Clear, byte or word
Reset Value: 0000h
MCPLL
15
Obj15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Obj14
Obj13
Obj12
Obj11
Obj10
Obj9
Obj8
Obj7
Obj6
Obj5
Obj4
Obj3
Obj2
Obj1
Obj0
TxERC (Tx Error Counter)
Address: MMR base + 274h
Access: Read, write, R/M/W, byte or word
Reset Value: 00h
TXERC
7
6
5
4
3
2
1
0
TC
7
TC
6
TC
5
TC
4
TC
3
TC
2
TC
1
TC
0
The Tx Error Counter can only be written to when the CAN Core is
in Reset mode. Hardware will preset the register to 128 when a
Bus–Off condition occurs. See the section entitled Bus Offon page
50 for details.
RxERC (Rx Error Counter)
Address: MMR base + 275h
Access: Read, write, R/M/W, byte or word
Reset Value: 00h
RXERC
7
6
5
4
3
2
1
0
RC
7
RC
6
RC
5
RC
4
RC
3
RC
2
RC
1
RC
0
The Rx Error Counter can only be written to when the CAN Core is
in Reset mode. When a Bus–Off condition occurs, this register is
cleared to 00h.
EWLR (Error Warning Limit Register)
Address: MMR base + 276h
Access: Read, write, R/M/W, byte or word
Reset Value: 96h
EWLR
7
6
5
4
3
2
1
0
EWL
7
EWL
6
EWL
5
EWL
4
EWL
3
EWL
2
EWL
1
EWL
0
ECCR (Error Code Capture Register)
Address: MMR base + 278h
Access: Read, write, R/M/W, byte or word
Reset Value: 00h
ECCR
7
6
5
4
3
2
1
0
EC1
EC0
State
The Error Code Capture Register contains detailed information
about the most recent Bus Error. See Table 25 for details. The
register must be read in order to be re–enabled for capturing the
next error code, as well as to clear the BERR status flag. This
register should be read before enabling the Bus Error interrupt.
ALCR (Arbitration Lost Capture Register)
Address: MMR base + 27Ah
Access: Read, write, R/M/W, byte or word
Reset Value: 00h
ALCR
7
–
6
–
5
–
4
3
2
1
0
Bit Number
The ALCR latches the bit number in the CAN Identifier where the
most recent Arbitration Lost occurred. See Table 26 for details. The
register must be read in order to be reenabled for capturing the next
arbitration lost code, as well as to clear the ARBLST status flag.
This register should be read before enabling the Arbitration Lost
interrupt.
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