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| 型號： | PXAC37 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| 中文描述： | 的XA 16位微控制器系列32K/1024檢察官可以傳輸層控制器1的UART，1個(gè)SPI端口，CAN 2.0B總線，32可以讀取器，傳輸層合作proce |
| 文件頁數(shù)： | 35/68頁 |
| 文件大?。?/td> | 368K |
| 代理商： | PXAC37 |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
28
AC ELECTRICAL CHARACTERISTICS
Table 20. AC Electrical Characteristics
V
DD
= 4.5V to 5.5V; T
amb
= 0 to +70
°
C for commercial, –40
°
C to +85
°
C for industrial.
SYMBOL
Figure
PARAMETER
VARIABLE CLOCK
UNIT
MIN
MAX
External Clock
f
C
t
C
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Address Cycle
t
CRAR
t
LHLL
t
AVLL
t
LLAX
Code Read Cycle
t
PLPH
t
LLPL
t
AVIVA
t
AVIVB
t
PLIV
t
PXIX
t
PXIZ
t
IXUA
Data Read Cycle
t
RLRH
t
LLRL
t
AVDVA
t
AVDVB
t
RLDV
t
RHDX
t
RHDZ
t
DXUA
Data Write Cycle
t
WLWH
t
LLWL
t
QVWX
t
WHQX
t
AVWL
t
UAWH
WAIT Input
t
WTH
t
WTL
Oscillator frequency
Clock period and CPU timing cycle
Clock high time
Clock low time
Clock rise time
Clock fall time
0
1/f
C
t
C
* 0.5
t
C
* 0.4
32
MHz
ns
ns
ns
ns
ns
22
22
22
22
22
5
5
21
16
16
16
Delay from clock rising edge to ALE rising edge
ALE pulse width (programmable)
Address valid to ALE de–asserted (set–up)
Address hold after ALE de–asserted
10
(V1 * t
C
) – 6
(V1 * t
C
) – 12
(t
C
/2) – 10
46
ns
ns
ns
ns
16
16
16
17
16
16
16
16
PSEN
/
pulse width
ALE de–asserted to PSEN
/
asserted
Address valid to instruction valid, ALE cycle (access time)
Address valid to instruction valid, non–ALE cycle (access time)
PSEN
/
asserted to instruction valid (enable time)
Instruction hold after PSEN
/
de–asserted
Bus 3–State after PSEN
/
de–asserted (disable time)
Hold time of unlatched part of address after instruction latched
(V2 * t
C
) – 10
(t
C
/2) – 7
ns
ns
ns
ns
ns
ns
ns
ns
(V3 * t
C
) – 36
(V4 * t
C
) – 29
(V2 * t
C
) – 29
0
t
C
– 8
0
18
18
18
19
18
18
18
18
RD
/
pulse width
ALE de–asserted to RD
/
asserted
Address valid to data input valid, ALE cycle (access time)
Address valid to data input valid, non–ALE cycle (access time)
RD
/
low to valid data in, enable time
Data hold time after RD
/
de–asserted
Bus 3–State after RD
/
de–asserted (disable time)
Hold time of unlatched part of address after data latched
(V7 * t
C
) – 10
(t
C
/2) – 7
ns
ns
ns
ns
ns
ns
ns
ns
(V6 * t
C
) – 36
(V5 * t
C
) – 29
(V7 * t
C
) – 29
0
t
C
– 8
0
20
20
20
20
20
20
WR
/
pulse width
ALE falling edge to WR
/
asserted
Data valid before WR
/
asserted (data setup time)
Data hold time after WR
/
de–asserted (Note 6)
Address valid to WR
/
asserted (address setup time) (Note 5)
Hold time of unlatched part of address after WR
/
is de–asserted
(V8 * t
C
) – 10
(V12 * t
C
) – 10
(V13 * t
C
) – 22
(V11 * t
C
) – 5
(V9 * t
C
) – 22
(V11 * t
C
) – 7
ns
ns
ns
ns
ns
ns
21
21
WAIT stable after bus strobe (RD
/
, WR
/
, or PSEN
/
) asserted
WAIT hold after bus strobe (RD
/
, WR
/
, or PSEN
/
) assertion
(V10 * t
C
) – 30
ns
ns
(V10 * t
C
) – 5
NOTES:
1.
Load capacitance for all outputs = 80pF.
2.
Variables V1 through V13 reflect programmable bus timing, which is
programmed via the Bus Timing registers (BTRH and BTRL).
Refer to the XA User Guide for details of the bus timing settings.
V1)
This variable represents the programmed width of the ALE pulse
as determined by the ALEW bit in the BTRL register.
V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.
V2)
This variable represents the programmed width of the PSEN
/
pulse
as determined by the CR1 and CR0 bits or the CRA1, CRA0, and
ALEW bits in the BTRL register.
–
For a bus cycle with
no
ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0
= 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during
burst mode code fetches, PSEN
/
does not exhibit transitions at
the boundaries of bus cycles. V2 still applies for the purpose of
determining peripheral timing requirements.
For a bus cycle
with
an ALE, V2 = the total bus cycle duration
(2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10,
and 5 if CRA1/0 = 11) minus the number of clocks used by
ALE (V1 + 0.5).
Example: If CRA1/0 = 10 and ALEW = 1, the V2 = 4 – (1.5 +
0.5) = 2.
This variable represents the programmed length of an entire code
read cycle
with
ALE. This time is determined by the CRA1 and
CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2
if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10,
and 5 if CRA1/0 = 11).
–
V3)
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