參數(shù)資料
型號: PXA270
廠商: Intel Corp.
英文描述: Electrical, Mechanical, and Thermal Specification
中文描述: 電氣,機械和熱規(guī)格
文件頁數(shù): 82/126頁
文件大?。?/td> 1563K
代理商: PXA270
6-18
Electrical, Mechanical, and Thermal Specification
Intel PXA270 Processor
AC Timing Specifications
6.4.3
ROM Parameters and Timing Diagrams
Table 6-16
lists the timings for ROM reads. See
Figure 6-11
,
Figure 6-12
,
Figure 6-13
, and
Figure 6-14
for timings diagrams representing burst and non-burst ROM reads.
Note:
Table 6-16
lists programmable register items. See the “Memory Controller” chapter in the
Intel
PXA27x Processor Family Developer’s Manual
for register configurations for more information on
these items.
Figure 6-10. SDRAM Fly-by DMA Timing
read
pre
nop
act
nop
write
nop
col
bank
row
col
rd0
rd1
rd2
rd3
wd0
wd1
wd2
wd3
0b0000
mask0
mask data bytes
mask1
mask2
mask3
drive data wd3
drive ddrive data wd2
drive data wd0
latch DVAL[1] asserted
latch data rd3
latch data rd2
latch data rd1
latch data rd0
1. MDCNFG[DTC] = 0b00 (CL = 2, tRP = 2 clk, tRCD = 1 clk)
2. See the SDRAM timing diagram.
Latch data on rising edge of SDCLK<1> when
DVAL<0> is asserted.
Using DVAL<1> driven two clocks early,
drive data on rising edge of SDCLK<2>.
SDCLK<1>
SDCLK<2>
SDCKE<1>
command
nSDCS<0>
nSDCS<2>
nSDRAS
nSDCAS
MA<24:10>
nWE
MD<31:0>
DQM<3:0>
RDnWR
DVAL<0>
DVAL<1>
NOTES:
Table 6-16. ROM AC Specification (Sheet 1 of 2)
Symbols
Parameters
MIN
TYP
MAX
Units
Notes
tromAS
Address setup to nCS assert
1
1
clk_mem
tromCES
nCS setup to nOE asserted
0
clk_mem
tromCEH
nCS hold from nOE deasserted
0
clk_mem
tromDSOH
MD setup to address valid
1.5
clk_mem
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