參數(shù)資料
型號(hào): PXA270
廠商: Intel Corp.
英文描述: Electrical, Mechanical, and Thermal Specification
中文描述: 電氣,機(jī)械和熱規(guī)格
文件頁數(shù): 107/126頁
文件大?。?/td> 1563K
代理商: PXA270
Electrical, Mechanical, and Thermal Specification
6-43
Intel PXA270 Processor
AC Timing Specifications
6.5
LCD Timing Specifications
Figure 6-28
describes the LCD timing parameters. The LCD pin timing specifications are
referenced to the pixel clock (L_PCLK_WR).
Table 6-22
gives the values for the parameters.
Figure 6-28. LCD Timing Definitions
Table 6-22. LCD Timing Specifications
Symbol
Description
Min
Max
Units
Notes
Tpclkdv
L_PCLK_WR rise/fall to L_LDD<17:0>
driven valid
14
ns
1
Tpclklv
L_PCLK_WR fall to L_LCLK_A0 driven
valid
14
ns
2
Tpclkfv
L_PCLK_WR fall to L_FCLK_RD driven
valid
14
ns
2
Tpclkbv
L_PCLK_WR rise to L_BIAS driven valid
14
ns
2
NOTES:
1. The LCD data pins can be programmed to be driven on either the rising or falling edge of the pixel clock
(L_PCLK_WR).
2. These LCD signals can toggle when L_PCLK_WR is not clocking (between frames). At this time, they are
clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK_WR pin.
L_LDD[17:0]
(rise)
L_LDD[17:0]
(fall)
L_PCLK_WR
L_LCLK_A0
L_BIAS
L_FCLK_RD
Tpclkdv
Tpclklv
Tpclkfv
Tpclkbv
Tpclkdv
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