- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383786 > PSD954F2V-90M (意法半導體) Flash In-System Programmable ISP Peripherals For 8-bit MCUs PDF資料下載
參數(shù)資料
| 型號： | PSD954F2V-90M |
| 廠商： | 意法半導體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設的8位微控制器 |
| 文件頁數(shù)： | 7/94頁 |
| 文件大?。?/td> | 476K |
| 代理商： | PSD954F2V-90M |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
Preliminary Information
PSD9XX Family
J
A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
Intel 8031, 80196, 80186, 80C251
Motorola 68HC11, 68HC16, 68HC12, and 683XX
Philips 8031 and 8051XA
Zilog Z80, Z8, and Z180
J
Internal 1 or 2 Mbit flash memory. This is the main Flash memory. It is divided into
eight equal-sized blocks that can be accessed with user-specified addresses.
J
Internal secondary 256 Kbit Flash memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash
concurrently.
J
16, 64 or 256 Kbit SRAM. The SRAM’s contents can be protected from a
power failure by connecting an external battery.
J
General Purpose PLD (GPLD) with 19 outputs. The GPLD may be used to implement
external chip selects or combinatorial logic function.
J
Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
J
27 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os.
16 of the I/O ports may be configured as open-drain outputs.
J
Standby current as low as 50 μA for 5 V devices.
J
Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the
field.
J
Internal page register that can be used to expand the microcontroller address space by
a factor of 256.
J
Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD9XX into Power Down Mode.
J
Erase/Write cycles:
Flash memory – 100,000 minimum
PLD – 1,000 minimum
Data Retention: 15 years
2.0
Key Features
3
相關PDF資料 |
PDF描述 |
|---|---|
| PSD954F2V-12JI | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD934F2 | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD934F2-70J | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD934F2-70M | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD934F2-90J | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PS-DA0104-01 | 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS |
| PS-DA0104-01S | 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS |
| PS-DA0105-01 | 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS |
| PS-DA0105-01S | 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS |
| PS-DA0105-03 | 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS |
發(fā)布緊急采購，3分鐘左右您將得到回復。