參數(shù)資料
型號： PSD834F2V
廠商： 意法半導體
英文描述： Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
中文描述： 閃光私營部門，3.3V電源，為8位微控制器2兆256千位雙閃存和64千位的SRAM
文件頁數(shù)： 17/89頁
文件大小： 615K
代理商： PSD834F2V
17/89
PSD834F2V
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
Write operation. The instruction is executed when
the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out period. Some instruc-
tions are structured to include Read operations af-
ter the initial Write operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into Read
mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 7:
Flash memory:
I
Erase memory by chip or sector
I
Suspend or resume sector erase
I
Program a Byte
I
Reset to Read mode
I
Read primary Flash Identifier value
I
Read Sector Protection Status
I
Bypass
These instructions are detailed in Table 7. For ef-
ficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address X555h during the first cycle and
data 55h to address XAAAh during the second cy-
cle. Address signals A15-A12 are Don’t Care dur-
ing the instruction Write cycles. However, the
appropriate
Sector
Select
CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0-
CSBOOT3) is High.
Power-down Instruction and Power-up Mode
Power-up Mode.
The PSD internal logic is reset
upon Power-up to the Read mode. Sector Select
(FS0-FS7 and CSBOOT0-CSBOOT3) must be
held Low, and Write Strobe (WR, CNTL0) High,
during Power-up for maximum security of the data
contents and to remove the possibility of a byte be-
ing written on the first edge of Write Strobe (WR,
(FS0-FS7
or
CNTL0). Any Write cycle initiation is locked when
V
CC
is below V
LKO
.
READ
Under typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using Read operations just as it would a
ROM or RAM device. Alternately, the MCU may
use Read operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these Read functions.
Read Memory Contents.
Primary Flash memory
and secondary Flash memory are placed in the
Read mode after Power-up, chip reset, or a Reset
Flash instruction (see Table 7). The MCU can read
the memory contents of the primary Flash memory
or the
secondary Flash memory by using Read op-
erations any time the Read operation is not part of
an instruction.
Read Primary Flash Identifier.
The
Flash memory identifier is read with an instruction
composed of 4 operations: 3 specific Write opera-
tions and a Read operation (see Table 7). During
the Read operation, address bits A6, A1, and A0
must be 0,0,1, respectively, and the appropriate
Sector Select (FS0-FS7) must be High. The iden-
tifier for the device is E7h.
Read Memory Sector Protection Status.
The
primary Flash memory Sector Protection Status is
read with an instruction composed of 4 operations:
3 specific Write operations and a Read operation
(see Table 7). During the Read operation, address
bits A6, A1, and A0 must be 0,1,0, respectively,
while Sector Select (FS0-FS7 or CSBOOT0-
CSBOOT3) designates the Flash memory sector
whose protection has to be verified. The Read op-
eration produces 01h if the Flash memory sector is
protected, or 00h if the sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem-
ory) can also be read by the MCU accessing the
Flash Protection registers in PSD I/O space. See
the section entitled “Flash Memory Sector Pro-
tect”, on page 22, for register definitions.
Reading the Erase/Program Status Bits.
The
PSD provides several status bits to be used by the
MCU to confirm the completion of an Erase or Pro-
gram cycle of Flash memory. These status bits
minimize the time that the MCU spends perform-
ing these tasks and are defined in Table 8. The
status bits can be read as many times as needed.
For Flash memory, the MCU can perform a Read
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
primary
相關PDF資料
PDF描述
PSD934F2V-20MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934F2V
PSD934F2V-15J Low Power Economy BiCMOS Current Mode PWM 8-TSSOP -40 to 85
PSD934F2V-15M Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934F2V-20JI Low Power Economy BiCMOS Current Mode PWM 8-TSSOP -40 to 85
相關代理商/技術參數(shù)
參數(shù)描述
PSD834F2V-15J 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2V-15M 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2V-20JI 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 200ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2V-20MI 功能描述:SPLD - 簡單可編程邏輯器件 3.0V 2M 200ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD835G2-70U 功能描述:靜態(tài)隨機存取存儲器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*