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參數(shù)資料
| 型號： | PSD834F2V |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM |
| 中文描述： | 閃光私營部門，3.3V電源，為8位微控制器2兆256千位雙閃存和64千位的SRAM |
| 文件頁數(shù)： | 13/89頁 |
| 文件大?。?/td> | 615K |
| 代理商： | PSD834F2V |
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PSD834F2V
Note: 1. The pin numbers in this table are for the PLCC package only. See the package information, on page 83 onwards, for pin numbers
on other package types.
2. These functions can be multiplexed with other functions.
PSD REGISTER DESCRIPTION AND ADDRESS OFFSET
Table 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.
PC5
13
I/O
PC5 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC5) output.
3. Input to the PLDs.
4. TDI input
2
for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC6
12
I/O
PC6 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC6) output.
3. Input to the PLDs.
4. TDO output
2
for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC7
11
I/O
PC7 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC7) output.
3. Input to the PLDs.
4. DBE – active Low Data Byte Enable input from 68HC912 type MCUs.
This pin can be configured as a CMOS or Open Drain output.
PD0
10
I/O
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input latches address output from the MCU.
2. MCU I/O – write or read from a standard output or input port.
3. Input to the PLDs.
4. CPLD output (External Chip Select).
PD1
9
I/O
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. Input to the PLDs.
3. CPLD output (External Chip Select).
4. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and
the CPLD AND Array.
PD2
8
I/O
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O
–
write to or read from a standard output or input port.
2. Input to the PLDs.
3. CPLD output (External Chip Select).
4. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/
O. When High, the PSD memory blocks are disabled to conserve power.
V
CC
15, 38
Supply Voltage
GND
1, 16,
26
Ground pins
Pin Name
Pin
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD934F2V-20MI | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD934F2V | |
| PSD934F2V-15J | Low Power Economy BiCMOS Current Mode PWM 8-TSSOP -40 to 85 |
| PSD934F2V-15M | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD934F2V-20JI | Low Power Economy BiCMOS Current Mode PWM 8-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD834F2V-15J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2V-15M | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2V-20JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 200ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2V-20MI | 功能描述:SPLD - 簡單可編程邏輯器件 3.0V 2M 200ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD835G2-70U | 功能描述:靜態(tài)隨機存取存儲器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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