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參數(shù)資料
| 型號： | PIC14000T-20I/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 63/153頁 |
| 文件大小： | 0K |
| 描述： | IC MCU OTP 4KX14 A/D 28SSOP |
| 產品培訓模塊： | Asynchronous Stimulus |
| 標準包裝： | 2,100 |
| 系列： | PIC® 14 |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C |
| 外圍設備： | POR，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 20 |
| 程序存儲器容量： | 7KB（4K x 14） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 192 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 6 V |
| 數(shù)據(jù)轉換器： | 斜率 A/D |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
| 配用： | 309-1025-ND - ADAPTER 28-SSOP TO 28-DIP |
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1996 Microchip Technology Inc.
Preliminary
DS40122B-page 17
PIC14000
4.2.2.1
STATUS REGISTER
The STATUS register, shown in Figure 4-3, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF
and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
“Instruction Set Summary.”
Note 1: The IRP and RP1 bits (STATUS<7:6>) are
not used by the PIC14000 and should be
programmed as cleared. Use of these bits
as general purpose R/W bits is NOT
recommended, since this may affect
upward compatibility with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
FIGURE 4-3:
STATUS REGISTER
83h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
Read/Write
R/W
R
R/W
POR value FFh
0
011
X
Bit
Name
Function
B7
IRP
Not used. This bit should be programmed as ‘0’.
Use of this bit as a general purpose read/write bit is not recommended, since this may
affect upward compatibility with future products.
B6
RP1
Not used. This bit should be programmed as ‘0’.
Use of this bit as a general purpose read/write bit is not recommended, since this may
affect upward compatibility with future products.
B5
RP0
Register page select for direct addressing.
1 = Bank1 (80h - FFh)
0 = Bank0 (00h - 7Fh)
Each page is 128 bytes. Only the RP0 bit is used.
B4
TO
Time-out bit.
1 = After power-up and by the CLRWDT and SLEEP instruction.
0 = A watchdog timer time-out has occurred.
B3
PD
Power down bit.
1 = After power-up or by a CLRWDT instruction.
0 = By execution of the SLEEP instruction.
B2
Z
Zero bit.
1 = The result of an arithmetic or logic operation is zero.
0 = The result of an arithmetic or logical operation is not zero.
B1
DC
Digit carry / borrow bit.
For ADDWF and ADDLW instructions.
1 = A carry-out from the 4th low order bit of the result.
0 = No carry-out from the 4th low order bit of the result.
Note: For Borrow, the polarity is reversed.
B0
C
Carry / borrow bit.
For ADDWF and ADDLW instructions.
1 = A carry-out from the most signicant bit of the result occurred. Note that a
subtraction is executed by adding the two’s complement of the second operand. For
rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
0 = No carry-out from the most signicant bit of the result.
Note: For Borrow the polarity is reversed.
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