Pericom Semiconductor 7. UART REGISTER DESCRIPTION............." />
參數(shù)資料
型號(hào)： PI7C9X7952AFDE
廠商： Pericom
文件頁(yè)數(shù)： 56/68頁(yè)
文件大?。?/td> 0K
描述： IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： PCIe至UART橋接
接口： 高級(jí)配置電源接口（ACPI）
電源電壓： 1.8V, 3.3V
封裝/外殼： 128-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤(pán)
安裝類(lèi)型： 表面貼裝
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 6 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
7.
UART REGISTER DESCRIPTION..................................................................................................42
7.1.
REGISTERS IN I/O MODE ..........................................................................................................42
7.1.1.
RECEIVE HOLDING REGISTER – OFFSET 00h ................................................................43
7.1.2.
TRANSMIT HOLDING REGISTER – OFFSET 00h..............................................................43
7.1.3.
INTERRUPT ENABLE REGISTER – OFFSET 01h ..............................................................43
7.1.4.
INTERRUPT STATUS REGISTER – OFFSET 02h................................................................44
7.1.5.
FIFO CONTROL REGISTER – OFFSET 02h .......................................................................44
7.1.6.
LINE CONTROL REGISTER – OFFSET 03h .......................................................................45
7.1.7.
MODEM CONTROL REGISTER – OFFSET 04h .................................................................45
7.1.8.
LINE STATUS REGISTER – OFFSET 05h ............................................................................46
7.1.9.
MODEM STATUS REGISTER – OFFSET 06h......................................................................47
7.1.10.
SPECIAL FUNCTION REGISTER – OFFSET 07h...............................................................47
7.1.11.
DIVISOR LATCH LOW REGISTER – OFFSET 00h, LCR[7] = 1 ........................................48
7.1.12.
DIVISOR LATCH HIGH REGISTER – OFFSET 01h, LCR[7] = 1.......................................48
7.1.13.
SAMPLE CLOCK REGISTER – OFFSET 02h, LCR[7] = 1 .................................................48
7.2.
REGISTERS IN MEMORY-MAPPING MODE.......................................................................................49
7.2.1.
RECEIVE HOLDING REGISTER – OFFSET 00h ................................................................50
7.2.2.
TRANSMIT HOLDING REGISTER – OFFSET 00h..............................................................51
7.2.3.
INTERRUPT ENABLE REGISTER – OFFSET 01h ..............................................................51
7.2.4.
INTERRUPT STATUS REGISTER – OFFSET 02h................................................................51
7.2.5.
FIFO CONTROL REGISTER – OFFSET 02h .......................................................................52
7.2.6.
LINE CONTROL REGISTER – OFFSET 03h .......................................................................52
7.2.7.
MODEM CONTROL REGISTER – OFFSET 04h .................................................................53
7.2.8.
LINE STATUS REGISTER – OFFSET 05h ............................................................................54
7.2.9.
MODEM STATUS REGISTER – OFFSET 06h......................................................................54
7.2.10.
SPECIAL FUNCTION REGISTER – OFFSET 07h...............................................................55
7.2.11.
DIVISOR LATCH LOW REGISTER – OFFSET 08h .............................................................55
7.2.12.
DIVISOR LATCH HIGH REGISTER – OFFSET 09h............................................................55
7.2.13.
ENHANCED FUNCTION REGISTER – OFFSET 0Ah.........................................................55
7.2.14.
XON SPECIAL CHARACTER 1 – OFFSET 0Bh...................................................................57
7.2.15.
XON SPECIAL CHARACTER 2 – OFFSET 0Ch ..................................................................57
7.2.16.
XOFF SPECIAL CHARACTER 1 – OFFSET 0Dh ................................................................57
7.2.17.
XOFF SPECIAL CHARACTER 2 – OFFSET 0Eh ................................................................57
7.2.18.
ADVANCE CONTROL REGISTER – OFFSET 0Fh ..............................................................57
7.2.19.
TRANSMIT INTERRUPT TRIGGER LEVEL – OFFSET 10h................................................58
7.2.20.
RECEIVE INTERRUPT TRIGGER LEVEL – OFFSET 11h ..................................................58
7.2.21.
FLOW CONTROL LOW TRIGGER LEVEL – OFFSET 12h .................................................58
7.2.22.
FLOW CONTROL HIGH TRIGGER LEVEL – OFFSET 13h ...............................................58
7.2.23.
CLOCK PRESCALE REGISTER – OFFSET 14h..................................................................58
7.2.24.
RECEIVE FIFO DATA COUNTER – OFFSET 15h, SFR[6] = 0..........................................58
7.2.25.
LINE STATUS REGISTER COUNTER – OFFSET 15h, SFR[6] = 1 ....................................59
7.2.26.
TRANSMIT FIFO DATA COUNTER – OFFSET 16h, SFR[7] = 1 .......................................59
7.2.27.
SAMPLE CLOCK REGISTER – OFFSET 16h, SFR[7] = 0 .................................................59
7.2.28.
GLOBAL LINE STATUS REGISTER – OFFSET 17h ............................................................59
7.2.29.
RECEIVE FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh..............................................60
7.2.30.
TRANSMIT FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh ...........................................60
7.2.31.
LINE STATUS FIFO REGISTERS –OFFSET 180h ~ 1FFh ..................................................60
8.
EEPROM INTERFACE .....................................................................................................................61
8.1.
AUTO MODE EERPOM ACCESS ...............................................................................................61
8.2.
EEPROM MODE AT RESET ........................................................................................................61
8.3.
EEPROM SPACE ADDRESS MAP AND DESCRIPTION ..........................................................61
13-0092
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