Pericom Semiconductor BIT FUNCTION TYPE DESCRIPTION 20 AUX Pow" />
參數(shù)資料
型號： PI7C9X7952AFDE
廠商： Pericom
文件頁數(shù)： 30/68頁
文件大?。?/td> 0K
描述： IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： PCIe至UART橋接
接口： 高級配置電源接口（ACPI）
電源電壓： 1.8V, 3.3V
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 36 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
20
AUX Power
Detected
RO
Asserted when the AUX power is detected by the I/O bridge
Reset to 1b.
21
Transactions
Pending
RO
It is not implemented. Hardwired to 0b.
31:22
Reserved
RO
Reset to 000h.
6.2.53. LINK CAPABILITIES REGISTER – OFFSET ECh
BIT
FUNCTION
TYPE
DESCRIPTION
3:0
Maximum Link
Speed
RO
Indicates the Maximum Link Speed of the given PCIe Link.
Defined encodings are: 0001b, which indicates 2.5 Gb/s Link
Reset to 1h.
9:4
Maximum Link
Width
RO
Indicates the maximum width of the given PCIe Link.
Reset to 000001b (x1).
11:10
Active State Power
Management
(ASPM) Support
RO
Indicates the level of ASPM supported on the given PCIe Link. The
I/O bridge supports L0s and L1 entry. The default value may be
changed by auto-loading from EEPROM.
Reset to 11b.
14:12
L0s Exit Latency
RO
Indicates the L0s exit latency for the given PCIe Link. The length of
time this I/O bridge requires to complete transition from L0s to L0 is
in the range of 256ns to less than 512ns. The default value may be
changed by auto-loading from EEPROM.
Reset to 011b.
17:15
L1 Exit
Latency
RO
Indicates the L1 exit latency for the given PCIe Link. The length of
time this I/O bridge requires to complete transition from L1 to L0 is
in the range of 16us to less than 32us. The default value may be
changed by auto-loading from EEPROM.
Reset to 000b.
23:18
Reserved
RO
Reset to 00000b.
31:24
Port Number
RO
It is not implemented. Hardwired to 00h.
6.2.54. LINK CONTROL REGISTER – OFFSET F0h
BIT
FUNCTION
TYPE
DESCRIPTION
1:0
Active State Power
Management
(ASPM) Control
RW
00b: ASPM is Disabled.
01b: L0s Entry Enabled.
10b: L1 Entry Enabled.
11b: L0s and L1 Entry Enabled.
Note that the receiver must be capable of entering L0s even when the
field is disabled.
Reset to 00b.
2
Reserved
RO
Reset to 0h.
3
Read Completion
Boundary (RCB)
RO
It is not implemented. Hardwired to 0b.
4
Link Disable
RO
It is not implemented. Hardwired to 0b.
5
Retrain Link
RO
It is not implemented. Hardwired to 0b.
6
Common Clock
Configuration
RW
0b: The components at both ends of a link are operating with
asynchronous reference clock.
1b: The components at both ends of a link are operating with a
distributed common reference clock.
Reset to 0b.
13-0092
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C9X7952AFDEX 制造商:Pericom Semiconductor Corporation 功能描述:
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PI7C9X7958AEVB 制造商:Pericom Semiconductor Corporation 功能描述:7958A EVAL BOARD 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD PI7C9X7958A 制造商:Pericom Semiconductor Corporation 功能描述:8 Port PCI Express UART I/O Bridge Evaluation Board
PI7C9X7958ANBE 功能描述:外圍驅(qū)動器與原件 - PCI X1 PCIE-UART 8 Channel Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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