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參數(shù)資料
| 型號： | PI7C7300DNAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 69/107頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 標準包裝： | 40 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 272-BBGA |
| 供應商設備封裝： | 272-PBGA（27x27） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 64 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
8.1
CONCURRENT LOCKS
The primary and secondary bus lock mechanisms operate concurrently except when a
locked transaction crosses PI7C7300D. A primary master can lock a primary target
without affecting the status of the lock on the secondary bus, and vice versa. This means
that a primary master can lock a primary target at the same time that a secondary master
locks a secondary target.
8.2
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300D
For any PCI bus, before acquiring access to the LOCK# signal and starting a series of
locked transactions, the initiator must first check that both of the following conditions are
met:
The PCI bus must be idle.
The LOCK# signal must be de-asserted.
The initiator leaves the LOCK# signal de-asserted during the address phase and asserts
LOCK# one clock cycle later. Once a data transfer is completed from the target, the
target lock has been achieved.
8.2.1
LOCKED TRANSACTIONS IN DOWSTREAM DIRECTION
Locked transactions can cross PI7C7300D only in the downstream direction, from the
primary bus to the secondary bus.
When the target resides on another PCI bus, the master must acquire not only the lock on
its own PCI bus but also the lock on every bus between its bus and the target’s bus.
When PI7C7300D detects on the primary bus, an initial locked transaction intended for a
target on the secondary bus, PI7C7300D samples the address, transaction type, byte
enable bits, and parity, as described in Section 4.6.4. It also samples the lock signal. If
there is a lock established between 2 ports or the target bus is already locked by another
master, then the current lock cycle is retried without forward. Because a target retry is
signaled to the initiator, the initiator must relinquish the lock on the primary bus, and
therefore the lock is not yet established.
The first locked transaction must be a memory read transaction. Subsequent locked
transactions can be memory read or memory write transactions. Posted memory write
transactions that are a part of the locked transaction sequence are still posted. Memory
read transactions that are a part of the locked transaction sequence are not pre-fetched.
When the locked delayed memory read request is queued, PI7C7300D does not queue
any more transactions until the locked sequence is finished. PI7C7300D signals a target
retry to all transactions initiated subsequent to the locked read transaction that are
intended for targets on the other side of PI7C7300D. PI7C7300D allows any transactions
queued before the locked transaction to complete before initiating the locked transaction.
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| PI7C8140AMAE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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