參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 57/107頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標準包裝： 40
系列： *
應用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應商設備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 53 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
-
The SERR# enable bit is set in the command register.
-
The parity error response bit is set in the command register.
When PI7C7300D detects an address parity error on the secondary interface, the
following events occur:
If the parity error response bit is set in the bridge control register, PI7C7300D does
not claim the transaction with S1_DEVSEL# or S2_DEVSEL#; this may allow the
transaction to terminate in a master abort. If parity error response bit is not set,
PI7C7300D proceeds normally and accepts transaction if it is directed to or across
PI7C7300D.
PI7C7300D sets the detected parity error bit in the secondary status register.
PI7C7300D asserts P_SERR# and sets signaled system error bit in status register, if
both of the following conditions are met:
-
The SERR# enable bit is set in the command register.
-
The parity error response bit is set in the bridge control register.
7.2
DATA PARITY ERRORS
When forwarding transactions, PI7C7300D attempts to pass the data parity condition
from one interface to the other unchanged, whenever possible, to allow the master and
target devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C7300D.
7.2.1
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C7300D detects a data parity error during a Type 0 configuration write
transaction to PI7C7300D configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C7300D asserts
P_TRDY# and writes the data to the configuration register. PI7C7300D also asserts
P_PERR#. If the parity error response bit is not set, PI7C7300D does not assert
P_PERR#.
PI7C7300D sets the detected parity error bit in the status register, regardless of the
state of the parity error response bit.
7.2.2
READ TRANSACTIONS
When PI7C7300D detects a parity error during a read transaction, the target drives data
and data parity, and the initiator checks parity and conditionally asserts PERR#.
For downstream transactions, when PI7C7300D detects a read data parity error on the
secondary bus, the following events occur:
相關PDF資料
PDF描述
PI7C8140AMAE IC PCI-PCI BRIDGE 2PORT 128-QFP
PI7C8150ANDE IC PCI-PCI BRIDGE 2PORT 256-PBGA
PI7C8150BNDIE IC PCI-PCI BRIDGE ASYNC 256-PBGA
PI7C8152BMAIE IC PCI-PCI BRIDGE 2PORT 160-MQFP
PI7C8154ANAE IC PCI-PCI BRIDGE ASYNC 304-PBGA
相關代理商/技術參數(shù)
參數(shù)描述
PI7C7300EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140AMA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge
PI7C8140AMAE 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*