參數(shù)資料
型號(hào): PI2EQX5904NJE
廠商: Pericom
文件頁(yè)數(shù): 4/23頁(yè)
文件大?。?/td> 0K
描述: IC PCIE 2.0 REDRIVER 100LBGA
標(biāo)準(zhǔn)包裝: 1
系列: PCI Express®(PCIe), ReDriver™
類型: 轉(zhuǎn)接驅(qū)動(dòng)器
驅(qū)動(dòng)器/接收器數(shù): 2/2
規(guī)程: PCIe? 2.0
電源電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 100-BGA
供應(yīng)商設(shè)備封裝: 100-LBGA(11x11)
包裝: 托盤(pán)
12
www.pericom.com
PS-0.5
10/18/10
All trademarks are property of their respective owners.
PI2EQX5904
5.0Gbps 4-Lane PCIe 2.0 ReDriver with Equalization & Emphasis
BYTE 3 - Channel Input Disable (INDIS)
INDIS_xy=0=enable input, INDIS_xy=1=disable input
Bit
7
6
5
4
3
2
1
0
Name
INDIS_A0
INDIS_B0
INDIS_A1
INDIS_B1
INDIS_A2
INDIS_B2
INDIS_A3
INDIS_B3
Type
R/W
Power-on
State
0
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Input Disable register, provides control over the input buffer of each channel independently. When and INDIS_xy
bit is logic 1, then the input buffer is switched off and the input termination is high impedance. This feature can be used for PCB
testing, and when only one input is used during Loopback as a demux function. When INDIS_xy is at a logic 0 state then the input
buffer is enabled (normal operating mode).
BYTE 4 - Channel Output Disable (OUTDIS)
ODIS_xy=0=enable output, ODIS_xy=1=disable output
Bit
7
6
5
4
3
2
1
0
Name
ODIS_A0
ODIS_B0
ODIS_A1
ODIS_B1
ODIS_A2
ODIS_B2
ODIS_A3
ODIS_B3
Type
R/W
Power-on
State
0
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Output Disable register, allows control over the output buffer of each channel independently. When and OUTDIS_xy
bit is logic 1, then the output buffer is switched off and the termination is high impedance. This feature can be used for PCB testing,
and when only one output is used during Loopback as a mux function. When INDIS_xy is at a logic 0 state then the input buffer is
enabled (normal operating mode).
BYTE 5 - Channel Reset (RESET)
RES_xy# =0=reset, RES_xy# =1=normal operation. Latch from RESET# input at startup
Bit
7
6
5
4
3
2
1
0
Name
RES_A0#
RES_B0#
RES_A1#
RES_B1#
RES_A2#
RES_B2#
RES_A3#
RES_B3#
Type
R/W
Power-on
State
RESET#
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition from 0 to 1 initiates a
new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled). While static at 0 or 1, the RES_zy# bit will have
no effect on operation. The Channel Reset bits are read/write allowing the current state to be checked.
10-0217
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