參數(shù)資料
型號(hào): PI2EQX5804CNJE
廠商: Pericom
文件頁(yè)數(shù): 5/23頁(yè)
文件大?。?/td> 0K
描述: IC PCI-E REDRIVER 100LBGA
標(biāo)準(zhǔn)包裝: 176
系列: ReDriver™
類(lèi)型: 轉(zhuǎn)接驅(qū)動(dòng)器
Tx/Rx類(lèi)型: CML
電容 - 輸入: 50pF
電源電壓: 1.15 V ~ 1.25 V
電流 - 電源: 800mA
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-BGA
供應(yīng)商設(shè)備封裝: 100-LBGA(11x11)
包裝: 托盤(pán)
13
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe 2.0 ReDriver with
Equalization & Emphasis
BYTE 3 - Channel Input Disable (INDIS)
INDIS_xy=0=enable input, INDIS_xy=1=disable input
Bit
76543210
Name
INDIS_A0
INDIS_B0
INDIS_A1
INDIS_B1
INDIS_A2
INDIS_B2
INDIS_A3
INDIS_B3
Type
R/W
Power-on
State
00000000
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The Channel Input Disable register, provides control over the input buffer of each channel independently.
When and INDIS_xy bit is logic 1, then the input buffer is switched off and the input termination is high im-
pedance. This feature can be used for PCB testing, and when only one input is used during Loopback as a de-
mux function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode).
BYTE 4 - Channel Output Disable (OUTDIS)
ODIS_xy=0=enable output, ODIS_xy=1=disable output
Bit
76543210
Name
ODIS_A0
ODIS_B0
ODIS_A1
ODIS_B1
ODIS_A2
ODIS_B2
ODIS_A3
ODIS_B3
Type
R/W
Power-on
State
00000000
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The Channel Output Disable register, allows control over the output buffer of each channel independently.
When and OUTDIS_xy bit is logic 1, then the output buffer is switched off and the termination is high imped-
ance. This feature can be used for PCB testing, and when only one output is used during Loopback as a mux
function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode).
BYTE 5 - Channel Reset (RESET)
RES_xy# =0=reset, RES_xy# =1=normal operation. Latch from RESET# input at startup
Bit
76543210
Name
RES_A0#
RES_B0#
RES_A1#
RES_B1#
RES_A2#
RES_B2#
RES_A3#
RES_B3#
Type
R/W
Power-on
State
RESET#
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition
from 0 to 1 initiates a new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled).
While static at 0 or 1, the RES_zy# bit will have no effect on operation. The Channel Reset bits are read/write
allowing the current state to be checked.
09-0001
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