SDA and SCL I/O for I
參數(shù)資料
型號: PI2EQX5804CNJE
廠商: Pericom
文件頁數(shù): 11/23頁
文件大?。?/td> 0K
描述: IC PCI-E REDRIVER 100LBGA
標(biāo)準(zhǔn)包裝: 176
系列: ReDriver™
類型: 轉(zhuǎn)接驅(qū)動器
Tx/Rx類型: CML
電容 - 輸入: 50pF
電源電壓: 1.15 V ~ 1.25 V
電流 - 電源: 800mA
安裝類型: 表面貼裝
封裝/外殼: 100-BGA
供應(yīng)商設(shè)備封裝: 100-LBGA(11x11)
包裝: 托盤
19
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe 2.0 ReDriver with
Equalization & Emphasis
SDA and SCL I/O for I2C-bus (VDD = 1.2 ± 0.05v, TA = 0 to 70°C)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VIH
DC input logic high
1.1
VDD+0.3
V
VIL
DC input logic low
-0.3
0.7
V
VOL
DC output logic low
IOL = 3mA
0.4
V
Vhys
Hysteresis of Schmitt trigger input
0.2
V
Characteristics of the SDA and SCL bus lines for F/S-mode I2C-bus devices(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
fSCL
SCL clock frequency
0
100
kHz
tHD;STA
Hold time (repeated) START condition. After
this period, the rst clock pulse is generated
4.0
μs
tLOW
LOW period of the SCL clock
4.7
μs
tHIGH
HIGH period of the SCL clock
4.0
μs
tSU;STA
Set-up time for a repeated START condition
4.7
μs
tHD;DAT
Data hold time
5.0
μs
tSU;DAT
Data set-up time
250
ns
tr
Rise time of both SDA and SCL signals
100
ns
tf
Fall time of both SDA and SCL signals
300
ns
tSU;STO
Set-up time for STOP condition
4.0
μs
tBUF
Buss free time between a STOP and STOP
condition
4.7
μs
Cb
Capacitive load for each bus line
400
pF
Notes:
1. All values referred to VIHmin and VILmax levels.
2. A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the unde-
ned region of the falling edge of SCL.
09-0001
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