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參數(shù)資料
| 型號(hào)： | PDM31548SA12SOATY |
| 廠商： | IXYS CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-44 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 226K |
| 代理商： | PDM31548SA12SOATY |
PDM31548
6
Rev. 1.3 - 4/13/98
PRELIMINARY
tAA
tRC
UB, LB
OE
CE
ADDRESSES
tOH
tAOE
tBA
DOUT
Output Data Valid
tLZBE(6)
tLZOE(6)
tLZCE(6)
tACE
tHZCE(6)
tHZOE(6)
tHZBE(6)
Read Timing Diagram(1)
AC Electrical Characteristics
NOTES: 1. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE.
2. tHZCE, tHZOE, and tHZWE are specied with CL = 5 pF as in Figure 2. Transition is measured ± 200 mV from
steady state voltage.
Description
–10
–12
–15
–20
READ Cycle
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
READ cycle time
tRC
10—12—15—20—
ns
Address access time
tAA
—10—12—15—20
ns
Chip enable access time
tACE
—10—12—15—20
ns
Byte access time
tBA
—6—7—8—9
ns
Output hold from address change
tOH
3—3—3—3—
ns
Byte disable to output in low-Z
tLZBE
0—0—0—0—
ns
Byte enable to output in high-Z
tHZBE
—7—8—9—9
ns
Chip enable to output in low-Z(1)
tLZCE
3—3—3—3—
ns
Chip disable to output high-Z(1, 2)
tHZCE
—6—7—8—9
ns
Output enable access time
tAOE
—6—7—8—9
ns
Output enable to output in low-Z
tLZOE
0—0—0—0—
ns
Output disable to output in high-Z(2)
tHZOE
—6—7—8—9
ns
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