參數(shù)資料
型號: PDM31548SA12SOATY
廠商: IXYS CORP
元件分類: SRAM
英文描述: 128K X 16 STANDARD SRAM, 12 ns, PDSO44
封裝: 0.400 INCH, PLASTIC, SOJ-44
文件頁數(shù): 1/9頁
文件大小: 226K
代理商: PDM31548SA12SOATY
Rev. 1.3 - 4/13/98
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PRELIMINARY
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PDM31548
Description
The PDM31548 is a high-performance CMOS static
RAM organized as 131,072 x 16 bits. The PDM31548
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM31548 operates from a single 3.3V power
supply and all inputs and outputs are fully TTL-
compatible.
The PDM31548 is available in a 44-pin 400-mil plas-
tic SOJ and a plastic TSOP (II) package for high-
density surface assembly and is suitable for use in
high-speed
applications
requiring
high-speed
storage.
PDM31548
128K x 16 CMOS
3.3V Static RAM
A8-A0
Memory
Cell
Array
256 x 128 x 32
Row
Address
Buffer
Control
Logic
Sense Amp
Column
Decoder
Column
Address
Buffer
Row
Decoder
Clock
Generator
A15-A9
CE
LB
UB
OE
WE
Data
Input/
Output
Buffer
Vcc
Vss
I/O15-I/O0
Features
n High-speed access times
- Com’l: 10, 12, 15 and 20 ns
- Ind: 12, 15 and 20 ns
n Low power operation (typical)
- PDM31548SA
Active: 250 mW
Standby: 25 mW
n High-density 128K x 16 architecture
n 3.3V (±0.3V) power supply
n Fully static operation
n TTL-compatible inputs and outputs
n Output buffer controls: OE
n Data byte controls: LB, UB
n Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Functional Block Diagram
512 x 128 x 32
A16 - A9
相關PDF資料
PDF描述
PDM31564SA8T 256K X 16 STANDARD SRAM, 8 ns, PDSO44
PDM41024SA10TTY 128K X 8 STANDARD SRAM, 10 ns, PDSO32
PDM41258SA7SO 64K X 4 STANDARD SRAM, 7 ns, PDSO24
PDM41298SA20TI 64K X 4 STANDARD SRAM, 20 ns, PDSO28
PDM42245L25GI 4K X 18 OTHER FIFO, CPGA68
相關代理商/技術參數(shù)
參數(shù)描述
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