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參數(shù)資料
| 型號： | PDI1394P21 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 3-port Physical Layer Interface(三端口物理層接口) |
| 中文描述： | 三端口物理層接口（三端口物理層接口） |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 148K |
| 代理商： | PDI1394P21 |
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Philips Semiconductors
Objective specification
PDI1394P21
3-port physical layer interface
1999 Jul 09
5
Name
Description
I/O
Pin Numbers
Pin Type
/RESET
CMOS 5V tol
78
I
Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to V
DD
is provided so only an external
delay capacitor in parallel with a resistor is required for proper power-up
operation. For more information, refer to Section 17.3. This input is
otherwise a standard logic input, and can also be driven by an
open-drain type driver.
R0, R1
Bias
66, 67
—
Current setting resistor terminals. These terminals are connected to
an external resistance to set the internal operating currents and
cable driver output currents. A resistance of 6.34 k
±
1% is required to
meet the IEEE Std 1394–1995 output voltage limits.
SYSCLK
CMOS
2
O
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
TEST0
CMOS
33
I
Test control input. This input is used in manufacturing tests of the
PDI1394P21. For normal use, this terminal should be tied to GND.
TEST1
CMOS
32
I
Test control input. This input is used in manufacturing tests of the
PDI1394P21. For normal use, this terminal should be tied to GND.
TPA0+,
TPA1+,
TPA2+
Cable
45, 52, 58
I/O
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential sig
matched and as short as possible to the external load resistors and to
the cable connector.
TPA0–,
TPA1–,
TPA2–
Cable
44, 51, 57
I/O
TPB0+,
TPB1+,
TPB2+
Cable
43, 50, 56
I/O
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential sig
matched and as short as possible to the external load resistors and to
the cable connector.
TPB0–,
TPB1–,
TPB2–
Cable
42, 49, 55
I/O
TPBIAS0,
TPBIAS1,
TPBIAS2
Cable
46, 53, 59
I/O
Twisted-pair bias output. This provides the 1.86V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. Each of these terminals must be decoupled with a
0.3
μ
F–1
μ
F capacitor to ground.
XO, XI
Crystal
77, 76
—
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394P21BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P22 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P22BD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P23 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-port/1-port 400 Mbps physical layer interface |
| PDI1394P23BD | 功能描述:IC IEEE 1394 LINK CTRLR 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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