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參數(shù)資料
| 型號(hào)： | PDI1394P21 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 3-port Physical Layer Interface(三端口物理層接口) |
| 中文描述： | 三端口物理層接口（三端口物理層接口） |
| 文件頁(yè)數(shù)： | 10/28頁(yè) |
| 文件大?。?/td> | 148K |
| 代理商： | PDI1394P21 |
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Philips Semiconductors
Objective specification
PDI1394P21
3-port physical layer interface
1999 Jul 09
10
12.0
OTHER DEVICE I/O
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
MAX
tbf
UNIT
mA
Peak
1
Transmit
2
Repeat
3
Idle
4
I
DD
Supply current
tbf
mA
tbf
mA
tbf
mA
I
DD–PD
Supply current in power down or
suspend mode
PD = V
DD
in power down mode
tbf
tbf
mA
V
TH
Cable power status threshold voltage
370 k
–400 k
resistor between cable
power and CPS pin: Measured at cable
power side of resistor
7.5
8.0
8.5
V
Hi h l
High-level
Dn, SYSCLK, CNA, C/LKON
t
t
lt
i
CTL
V
DD
>= 2.7 V, I
OH
= –4 mA, /ISO = V
DD
V
DD
>= 3.0 V, I
OH
= –4 mA, /ISO = V
DD
Annex J: I
OH
= –9 mA, /ISO = 0
I
OL
= 4 mA, /ISO = V
DD
Annex J: I
OL
= 9 mA, /ISO = 0
/ISO = V
DD
, V
I
= 0 V to V
DD
/ISO = V
DD
, V
I
= 0 V to V
DD
2.2
V
V
OH
2.8
V
V
DD
–0.4
V
V
OL
Low level output voltage
Low-level output voltage
0.4
V
0.4
V
I
BH+
I
BH–
Positive peak bus holder current
0.08
0.25
mA
Negative peak bus holder current
–0.25
–0.08
mA
I
I
Input current, pins LREQ, LPS, PD,
TEST0, TEST1, PC0–PC2
Off-state current, pins CTLn, Dn,
C/LKON
/ISO = 0 V; V
DD
= 3.6 V
5
μ
A
I
OZ
VO = V
DD
or 0 V
–5
5
μ
A
I
RST-UP
Pullup current /RESET input
Pullup current, /RESET input
V
I
= 1.5 V, PD = 0
V
I
= 0 V, PD = 0
V
I
= V
DD
, PD = V
DD
–80
–40
–20
μ
A
μ
A
μ
A
–90
–45
–22
I
RST-DN
Pulldown current, /RESET input
86
260
450
V
IT+
Positive going threshold voltage, LREQ,
CTL0, CTL1, D0–D7, C/LKON inputs
5
Negative going threshold voltage, LREQ,
CTL0, CTL1, D0–D7, C/LKON inputs
5
Positive going threshold voltage, PD,
LPS inputs
Negative going threshold voltage, PD,
LPS inputs
TPBIAS output voltage
/ISO = 0 V
V
DD
/2 + 0.3
V
DD
/2 + 0.9
V
V
IT–
/ISO = 0 V
V
DD
/2 – 0.9
V
DD
/2 – 0.3
V
V
IT+
/ISO = 0 V. V
LREF
= 0.42 x V
DD
V
LREF
+1
V
V
IT–
/ISO = 0 V. V
LREF
= 0.42 x V
DD
V
LREF
+0.2
V
V
O
NOTES:
1. Worst case, all ports transmitting, 100% bandwidth at S400, V
DD
= 3.6 V, T
A
= 0
°
C: At T
A
= 70
°
C, the maximum current is tbf mA.
2. All ports transmitting, 100% bandwidth at S400, V
DD
= 3.3 V, T
A
= 25
°
C
3. Receiving on port 0 and transmitting on port 1 and port 2. Full ISO payload of 84
μ
S, S400, data value of CCCCCCCCh, V
DD
= 3.3 V, TA = 25
°
C
4. Receiving cycle starts on port 0 and transmitting cycle starts on port 1 and port 2, V
DD
= 3.3 V, TA = 25
°
C
5. C/LKON is only an input when /RESET = 0
At rated I
O
current
1.665
2.015
V
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