參數(shù)資料
型號(hào): PDI1394P21
廠商: NXP Semiconductors N.V.
英文描述: 3-port Physical Layer Interface(三端口物理層接口)
中文描述: 三端口物理層接口(三端口物理層接口)
文件頁(yè)數(shù): 3/28頁(yè)
文件大?。?/td> 148K
代理商: PDI1394P21
Philips Semiconductors
Objective specification
PDI1394P21
3-port physical layer interface
1999 Jul 09
3
4.0
PIN CONFIGURATION
N
1
2
3
4
5
6
7
23
24
25
26
27
28
29
LREQ
SYSCLK
DGND
CTL0
CTL1
D0
DVDD
30
31
21
22
8
9
10
11
D1
NC
D3
D2
PDI1394P21
12
13
14
15
16
17
D4
D5
D6
D7
CNA
DGND
18
19
20
PD
LPS
DGND
32
33
34
35
36
D
C
P
P
P
/
C
D
D
D
N
T
T
A
A
A
60
59
58
57
56
55
54
AGND
TPBIAS2
TPA2+
TPA2–
TPB2+
AVDD
TPB2–
53
52
51
50
TPBIAS1
TPA1+
TPB1+
TPA1–
49
48
47
46
45
44
TPB1–
AVDD
AVDD
TPBIAS0
TPA0–
TPA0+
43
42
41
TPB0+
TPB0–
AGND
78
77
76
75
74
73
72
71
70
80
79
69
68
67
66
65
D
D
/
X
X
P
P
P
N
D
D
D
R
R
A
37
38
39
40
64
63
62
61
A
A
A
A
A
A
A
A
SV001742
5.0
PIN DESCRIPTION
Name
Pin Type
Pin Numbers
I/O
Description
AGND
Supply
36, 37, 38, 39, 40,
41, 60, 61, 64, 65
Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
AVDD
Supply
34, 35, 47, 48, 54,
62, 63
Analog circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1
μ
F and 0.001
μ
F. Lower frequency 10
μ
F filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and DVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
CNA
CMOS
17
O
Cable Not Active output. This terminal is asserted high when there are
no ports receiving incoming bias voltage.
CPS
CMOS
27
I
Cable Power Status input. This terminal is normally connected to cable
power through a 370–410 k
resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
CTL0,
CTL1
CMOS 5V tol
4, 5
I/O
Control I/Os. These bi-directional signals control communication
between the PDI1394P21 and the LLC. Bus holders are built into
these terminals.
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