參數資料
| 型號： | PCX7447AVGH1000NB |
| 廠商： | Atmel |
| 文件頁數： | 34/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 1000MHZ 360CBGA |
| 標準包裝： | 44 |
| 處理器類型： | PowerPC 32-位 RISC |
| 速度： | 1.0GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CBBGA 裸露焊盤 |
| 供應商設備封裝： | 360-CBGA（25x25） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
4
0833E–HIREL–01/07
PC7447A
e2v semiconductors SAS 2007
Thirty-two 64-bit FPRs for single- or double-precision operands
– Four vector units and 32-entry vector register file (VRs)
Vector permute unit (VPU)
Vector integer unit 1 (VIU1) handles short-latency AltiVec integer instructions, such as
vector add instructions (for example, vaddsbs, vaddshs, and vaddsws).
Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and vmladduhm).
Vector floating-point unit (VFPU)
– Three-stage load/store unit (LSU)
Supports integer, floating-point, and vector instruction load/store traffic
Four-entry vector touch queue (VTQ) supports all four architectures of the AltiVec data
stream operations
Three-cycle GPR and AltiVec load latency (byte, half word, word, vector) with one-cycle
throughput
Four-cycle FPR load latency (single, double) with one-cycle throughput
No additional delay for misaligned access within double-word boundary
Dedicated adder calculates effective addresses (EAs)
Supports store gathering
Performs alignment, normalization, and precision conversion for floating-point data
Executes cache control and TLB instructions
Performs alignment, zero padding, and sign extension for integer data
Supports hits under misses (multiple outstanding misses)
Supports both big- and little-endian modes, including misaligned little-endian accesses
Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,
respectively, in a cycle. Instruction dispatch requires the following:
– Instructions can only be dispatched from the three lowest IQ entries: IQ0, IQ1, and IQ2
– A maximum of three instructions can be dispatched to the issue queues per clock cycle
– Space must be available in the CQ for an instruction to dispatch (this includes instructions
that are assigned a space in the CQ but not in an issue queue)
相關PDF資料 |
PDF描述 |
|---|---|
| IDT70V07L55J8 | IC SRAM 256KBIT 55NS 68PLCC |
| IDT7007L55J8 | IC SRAM 256KBIT 55NS 68PLCC |
| ASC19DTEN | CONN EDGECARD 38POS .100 EYELET |
| ASC19DTEH | CONN EDGECARD 38POS .100 EYELET |
| AMC18DTEN | CONN EDGECARD 36POS .100 EYELET |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PCX7447AVGH1167NB | 功能描述:IC MPU 32BIT 1167MHZ 360CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:60 系列:SCC 處理器類型:Z380 特點:全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應商設備封裝:144-LQFP 包裝:托盤 |
| PCX7448MGH1000NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
| PCX7448MGH1250NC | 制造商:e2v technologies 功能描述:PCX7448MGH1250NC - Trays |
| PCX7448VGH1000NC | 制造商:e2v technologies 功能描述:PCX7448VGH1000NC - Trays |
| PCX7448VGH1250NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1.25GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。