參數(shù)資料
型號: PCX7447AVGH1000NB
廠商: Atmel
文件頁數(shù): 2/52頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 1000MHZ 360CBGA
標準包裝: 44
處理器類型: PowerPC 32-位 RISC
速度: 1.0GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 360-CBBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 360-CBGA(25x25)
包裝: 托盤
10
0833E–HIREL–01/07
PC7447A
e2v semiconductors SAS 2007
6.3
Recommended Operating Conditions
Table 6-2 provides the recommended operating conditions for the PC7447A.
Notes:
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not
guaranteed.
2. This voltage is the input to the filter discussed in Section “PLL Power Supply Filtering” on page 41 and not necessarily the
voltage at the AVDD pin, which may be reduced from VDD by the filter.
Figure 6-1.
Overshoot/Undershoot Voltage
The PC7447A provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The PC7447A core voltage must always be provided at a nominal 1.3V (see
Table 6-2 on page 10 for the actual recommended core voltage). The input voltage threshold for each
bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET.
The output voltage will swing from GND to the maximum voltage applied to the OVDD power pins. Table
6-3 on page 11 provides the input threshold voltage settings. Because these settings may change in
future products, it is recommended that BVSEL be configured using resistor options, jumpers, or some
other flexible means, with the capability to reconfigure the termination of this signal in the future if
necessary.
Table 6-2.
Recommended Operating Conditions(1)
Symbol
Characteristic
Recommended Value
Unit
Min
Max
VDD
Core supply voltage
1.3V ± 50 mV or 1.1V ± 50 mV
V
AV
DD
PLL supply voltage
1.3V ± 50 mV or 1.1V ± 50 mV
V
OVDD
Processor bus supply
voltage
BVSEL = 0
1.8V ± 5%
V
OVDD
BVSEL = HRESET or
OV
DD
2.5V ± 5%
VIN
Input voltage
Processor bus
GND
OVDD
V
VIN
JTAG signals
GND
OVDD
T
J
Die-junction temperature
-55
125°C
°C
GND
GND – 0.3V
GND – 0.7V
Not to exceed 10% of tSYSCLK
OVDD + 20%
OVDD + 5%
OVDD
VIH
VIL
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