參數(shù)資料
型號(hào): PCX7447AVGH1000NB
廠商: Atmel
文件頁數(shù): 12/52頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 1000MHZ 360CBGA
標(biāo)準(zhǔn)包裝: 44
處理器類型: PowerPC 32-位 RISC
速度: 1.0GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 360-CBBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 360-CBGA(25x25)
包裝: 托盤
2
0833E–HIREL–01/07
PC7447A
e2v semiconductors SAS 2007
1.
Block Diagram
Figure 1-1.
PC7447A Microprocessor Block Diagram
Additional
Features
Time
Base
Counter/Decrementer
Clock
Multiplier
JTAG/COP
Interface
Thermal/Power
Management
Performance
Monitor
Dynamic
Frequency
Switching
(DFS)
Temperature
Dioder
+
x
÷
F
PSCR
F
PSCR
PA
+
x
÷
In
st
ru
ct
io
n
Un
it
Instruction
Queue
(12-Word)
96
-B
it(
3I
nstr
uctio
ns)
R
eser
vat
io
n
32-Bit
Flo
at
ing
-
Po
in
tUnit
64
-Bi
t
Load/Store
Unit
(E
A
Ca
lc
ulat
io
n)
F
inish
ed
32
-Bi
t
Completion
Unit
(16-Entry)
36-bit
64-bit
S
tatio
ns
(
2)
FP
R
F
ile
16
Rena
me
Bu
ffe
rs
G
P
R
F
ile
16
Ren
ame
Buffer
s
VR
Fil
e
16
Rena
me
B
uf
fers
64
-Bi
t
128
-Bi
t
12
8-Bi
t
Co
m
ple
te
su
p
SRs
(Shadow)
128-Entry
ITLB
St
or
es
Lo
ad
Mi
ss
CTR
LR
V
ec
tor
T
ou
ch
E
ng
ine
32-Bit
EA
L1
Castout
Status
L2
Store
Queue
(L2SQ)
Vector
FPU
Vector
Integer
Unit
1
Vector
Integer
Unit
2
Vector
Permute
Unit
Status
Block
1
(32-Byte)
Memory
Subsystem
Snoop
Push/
Interventions
L1
Castouts
Bus
Accumulator
L1
Push
(4)
to
thr
ee
pe
rclock
in
st
ru
ct
io
ns
L1
Load
Queue
(LLQ)
L1
Load
Miss
(5)
Instruction
Fetch
(2)
Cacheable
Store
Request
(1)
L1
Service
Queues
L1
Store
Queue
(LSQ)
L2
Prefetch
(3)
Address
Bus
Data
Bus
Castout
Queue
(9)
/
Push
Queue
(10)
2
Bus
Store
Queue
Load
Queue
(11)
Completion
Queue
Reservation
Station
Reservation
Station
Reservation
Station
Reservation
Station
Branc
h
Pr
ocessing
Unit
BTIC
(128-Entr
y)
BHT
(2048-Entr
y)
VR
Issue
(4-Entry/2-Issue)
GPR
Issue
(6-Entry/3-Issue)
FPR
Issue
(2-Entry/1-Issue)
Fetcher
Dispatch
Unit
Instruction
MMU
IBAT
Array
Data
MMU
DBAT
Array
128-Bit
(4
Instructions)
Tags
32-Kbyte
ICache
32-Kbyte
D
Cache
Tags
SRs
(Original)
128-Entry
DTLB
Reservation
Stations
(2-Entry)
Vector
Touch
Queue
Completed
Stores
512-Kbyte
Unified
L2
Cache
Controller
Line
Tags
Block
0
(32-Byte)
System
Bus
Interface
Notes:
The
castout
queue
and
push
queue
share
resources
such
for
a
combined
total
of
entries.
The
castout
queue
itself
is
limited
to
9
entries,
ensuring
1
entry
will
be
available
for
a
push.
Integ
er
Unit
2
Reser
vation
Stations
(2)
Reservation
Station
Integ
er
Unit
1
(3)
+
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