參數(shù)資料
型號(hào)： PCM9211PT
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： DATACOM, TOKEN RING TRANSCEIVER, PQFP48
封裝： GREEN, PLASTIC, LQFP-48
文件頁(yè)數(shù)： 75/121頁(yè)
文件大?。?/td> 1219K
代理商： PCM9211PT
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9
SDA
SCL
St
Start
condition
1 – 7
8
1 – 8
9
1 – 8
9
Sp
Stop
condition
Slaveaddress
R/W
ACK
DATA
ACK
DATA
ACK
R/W:
Read
o perationif1; otherwise, write operation
ACK:
Acknowledgementofa byteif0, n ot Acknowledgementofabiteif1
DATA:
8 b its( byte) ,Detailsaredescribedinwriteandreadoperation
.
www.ti.com
SBAS495 – JUNE 2010
Packet Protocol
A master device must control the packet protocol, which consists of a start condition, slave address with
read/write bit, data if a write procedure is desired, or an acknowledgment if read and stop conditions exist. The
PCM9211 supports both slave receiver and transmitter functions. Details of the DATA pulse for both write and
read operations are described in Figure 40.
Figure 40. I2C Packet Protocol
Write Operation
The PCM9211 can only function as an I2C slave. A master can write to any PCM9211 registers using either
single or multiple accesses. The master sends a PCM9211 slave address with a write bit, a register address, and
the data. When undefined registers are accessed, the PCM9211 does not send an acknowledgment. Figure 41
illustrates the write operation. The register address and the write data are 8-bit, MSB-first format.
Transmitter
M
S
M
S
M
S
M
S
M
Data Type
St
slave
W
ACK
reg
ACK
write
ACK
write
ACK
Sp
address
data 1
data 2
M: Master Device S: Slave Device St: Start Condition W: Write ACK: Acknowledge Sp: Stop Condition
Figure 41. Framework for Write Operation
Read Operation
A master can read the PCM9211 registers. The value of the register address is stored in an indirect index
register in advance. The master sends the PCM9211 slave address with a read bit after storing the register
address. The PCM9211 then transfers the data to which the index register points. Figure 42 shows the read
operation.
Transmitter
M
S
M
S
M
S
M
Data Type
St
slave
W
ACK
reg address
ACK
Sr
slave address
R
ACK
read
NACK
Sp
address
data
M: Master Device S: Slave Device St: Start Condition Sr: Repeated Start Condition W: Write R: Read
ACK: Acknowledge NACK: Not Acknowledge Sp: Stop Condition
Note:
The slave address after the repeated start condition must be the same as the previous slave address.
Figure 42. Framework for Read Operation
Copyright 2010, Texas Instruments Incorporated
57
Product Folder Link(s): PCM9211
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