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PIC18F46J50 FAMILY
DS39931D-page 174
2011 Microchip Technology Inc.
REGISTER 11-5:
PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h)(1)
R/W-0
—PTEN14
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented:
Maintain as ‘0’
bit 6
PTEN14:
PMCS Port Enable bit
1
= PMCS chip select line
0
= PMCS functions as port I/O
bit 5-0
Unimplemented:
Maintain as ‘0’
Note 1:
This register is only available on 44-pin devices.
REGISTER 11-6:
PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE (BANKED F56h)(1)
R/W-0
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
PTEN<7:2>:
PMP Address Port Enable bits
1
= PMA<7:2> function as PMP address lines
0
= PMA<7:2> function as port I/O
bit 1-0
PTEN<1:0>:
PMALH/PMALL Strobe Enable bits
1
= PMA<1:0> function as either PMA<1:0> or PMALH and PMALL
0
= PMA<1:0> pads function as port I/O
Note 1:
This register is only available on 44-pin devices.