參數(shù)資料
型號(hào)： PCM18XT0
廠(chǎng)商： Microchip Technology
文件頁(yè)數(shù)： 139/183頁(yè)
文件大小： 0K
描述： MODULE PROC PIC18F4685
標(biāo)準(zhǔn)包裝： 1
附件類(lèi)型： 處理器模塊
適用于相關(guān)產(chǎn)品： ICE2000
產(chǎn)品目錄頁(yè)面： 658 (CN2011-ZH PDF)
配用： ICE2000-ND - EMULATOR MPLAB-ICE 2000 POD
相關(guān)產(chǎn)品： DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD
DVA18PQ440-ND - DEVICE ADAPTER 18F4220 TQFP 44LD
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2011 Microchip Technology Inc.
DS39931D-page 59
PIC18F46J50 FAMILY
REGISTER 4-5:
DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh)
U-0
R/W-0
—
—DSINT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
Unimplemented:
Read as ‘0’
bit 0
DSINT0:
Interrupt-on-Change bit
1
= Interrupt-on-change was asserted during Deep Sleep
0
= Interrupt-on-change was not asserted during Deep Sleep
REGISTER 4-6:
DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah)
R/W-0
U-0
R/W-0
U-0
R/W-1
DSFLT
—
DSULP
DSWDT
DSRTC
DSMCLR
—
DSPOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
DSFLT:
Deep Sleep Fault Detected bit
1
= A Deep Sleep Fault was detected during Deep Sleep
0
= A Deep Sleep Fault was not detected during Deep Sleep
bit 6
Unimplemented:
Read as ‘0’
bit 5
DSULP:
Ultra Low-Power Wake-up Status bit
1
= An Ultra Low-Power Wake-up event occurred during Deep Sleep
0
= An Ultra Low-Power Wake-up event did not occur during Deep Sleep
bit 4
DSWDT:
Deep Sleep Watchdog Timer Time-out bit
1
= The Deep Sleep Watchdog Timer timed out during Deep Sleep
0
= The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3
DSRTC:
Real-Time Clock and Calendar Alarm bit
1
= The Real-Time Clock/Calendar triggered an alarm during Deep Sleep
0
= The Real-Time Clock /Calendar did not trigger an alarm during Deep Sleep
bit 2
DSMCLR:
MCLR Event bit
1
= The MCLR pin was asserted during Deep Sleep
0
= The MCLR pin was not asserted during Deep Sleep
bit 1
Unimplemented:
Read as ‘0’
bit 0
DSPOR:
Power-on Reset Event bit
1
= The VDD supply POR circuit was active and a POR event was detected(1)
0
= The VDD supply POR circuit was not active, or was active, but did not detect a POR event
Note 1:
Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
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