參數(shù)資料
型號(hào)： PCF85176T
廠商： NXP SEMICONDUCTORS
元件分類： 顯示驅(qū)動(dòng)器
英文描述： Universal LCD driver for low multiplex rates
中文描述： LIQUID CRYSTAL DISPLAY DRIVER, PDSO56
封裝： 6.10 MM, PLASTIC, MO-153, SOT364-1, TSSOP-56
文件頁(yè)數(shù)： 27/47頁(yè)
文件大?。?/td> 405K
代理商： PCF85176T
PCF85176
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 27 June 2011
27 of 47
NXP Semiconductors
PCF85176
Universal LCD driver for low multiplex rates
8.5 I
2
C-bus controller
The PCF85176 acts as an I
2
C-bus slave receiver. It does not initiate I
2
C-bus transfers or
transmit data to an I
2
C-bus master receiver. The only data output from the PCF85176 are
the acknowledge signals of the selected devices. Device selection depends on the
I
2
C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to V
SS
which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to V
SS
or V
DD
using a binary coding scheme, so that
no two devices with a common I
2
C-bus slave address have the same hardware
subaddress.
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.7 I
2
C-bus protocol
Two I
2
C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCF85176. The entire I
2
C-bus slave address byte is shown in
Table 16
.
Table 16.
The PCF85176 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte that a PCF85176 will respond to,
is defined by the level tied to its SA0 input (V
SS
for logic 0 and V
DD
for logic 1).
Having two reserved slave addresses allows the following on the same I
2
C-bus:
Up to 16 PCF85176 for very large LCD applications
The use of two types of LCD multiplex drive
The I
2
C-bus protocol is shown in
Figure 18
. The sequence is initiated with a START
condition (S) from the I
2
C-bus master which is followed by one of two possible PCF85176
slave addresses available. All PCF85176 whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I
2
C-bus transfer is
ignored by all PCF85176 whose SA0 inputs are set to the alternative level.
I
2
C slave address byte
Slave address
7
6
MSB
0
1
Bit
5
4
3
2
1
0
LSB
R/W
1
1
0
0
SA0
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