PCF85176
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 27 June 2011
20 of 47
NXP Semiconductors
PCF85176
Universal LCD driver for low multiplex rates
7.10.3
RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in
Table 6
(see
Figure 13
as
well).
Table 6.
Assumption: BP2/S2, BP2/S5, BP2/S8 etc.
are not connected
to any elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
0
a7
a4
a1
b7
1
a6
a3
a0
b6
2
a5
a2
-
b5
3
-
-
-
-
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in
Table 7
.
Table 7.
Assumption: BP2/S2, BP2/S5, BP2/S8 etc.
are connected
to elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
0
a7
a4
a1/b7 b4
1
a6
a3
a0/b6 b3
2
a5
a2
b5
b2
3
-
-
-
-
In the case described in
Table 7
the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
In the first write to the RAM, bits a7 to a0 are written.
In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
7.10.4
Writing over the RAM address boundary
In all multiplex drive modes, depending on the setting of the data pointer, it is possible to
fill the RAM over the RAM address boundary. If the PCF85176 is part of a cascade the
additional bits fall into the next device that also generates the acknowledge signal. If the
PCF85176 is a single device or the last device in a cascade the additional bits will be
discarded and no acknowledge signal will be generated.
Standard RAM filling in 1:3 multiplex drive mode
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
b4
b3
b2
-
b1
b0
-
-
c7
c6
c5
-
c4
c3
c2
-
c1
c0
-
-
d7
d6
d5
-
:
:
:
:
Entire RAM filling by rewriting in 1:3 multiplex drive mode
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
b1/c7 c4
b0/c6 c3
c5
-
c1/d7 d4
c0/d6 d3
d5
-
d1/e7 e4
d0/e6 e3
e5
-
:
:
:
:
c2
-
d2
-
e2
-