2001 Dec 19
34
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2113x
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition.
10.2.1
I
2
C-
BUS PROTOCOL
Before any data is transmitted on the I
2
C-bus, the device
whichshouldrespondisaddressedfirst.Theaddressingis
always carried out with the first byte transmitted after the
START procedure. The I
2
C-bus configuration for the
different PCF2113x read and write cycles is shown in
Figs 24 to 26. The slow down feature of the I
2
C-bus
protocol (receiver holds SCL LOW during internal
operations) is not used in the PCF2113x.
10.2.2
D
EFINITIONS
Transmitter: the device which sends the data to the bus
Receiver: the device which receives the data from the
bus
Master: the device which initiates a transfer generates
clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronization: procedure to synchronize the clock
signals of two or more devices.
MGA807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig.20 System configuration.
handbook, full pagewidth
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.21 Bit transfer.